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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Interposer for semiconductor package assembly

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H05K-001/16    H05K-007/02   
미국특허분류(USC) 174/260; 174/261; 174/262; 361/760; 257/686; 257/738; 257/778
출원번호 US-0499801 (2000-02-08)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Beyer, Weaver & Thomas LLP
인용정보 피인용 횟수 : 56  인용 특허 : 10
초록
▼

The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal st...

대표
청구항

1. A semiconductor package, comprising:a packaging substrate including a ceramic material; a die mechanically bound to said packaging substrate and in electrical communication with said packaging substrate; an interposer mechanically bound and in electrical communication with said packaging substrate, said interposer including an array of conductive links traversing from a first face of said interposer to a second face of said interposer; and an underfill material deposited at least partially between said packaging substrate and said interposer.

이 특허에 인용된 특허 (10)

  1. Turturro Gregory. C4-GT stand off rigid flex interposer method. USP2000076088915.
  2. Lee Michael Guang-Tzong ; Beilin Solomon I. ; Wang Wen-chou Vincent. Chip and board stress relief interposer. USP2000046050832.
  3. Iwasaki Ken,JPX. Electronic device and semiconductor package. USP1998115834848.
  4. Nguyen Hung N. (Bensalem PA). Electronic device interconnection techniques. USP1995125477933.
  5. Brodsky William Louis ; Kehley Glenn Lee ; Myrto Glenn Edward ; Sherman John Henry. Flexible circuitized interposer with apertured member and method for making same. USP1998065759047.
  6. Bellaar Pieter H.,NLX ; DiStefano Thomas H. ; Fjelstad Joseph ; Pickett Christopher M. ; Smith John W.. Microelectronic component with rigid interposer. USP1999126002168.
  7. Ikeda Hironobu,JPX ; Yamaguti Yukio,JPX. Mounting structure for one or more semiconductor devices. USP1999105973930.
  8. Stone David B. (Owego NY). Passive interposer including at least one passive electronic component. USP1996065530288.
  9. Kresge John S. ; Moore Scott P. ; Susko Robin A. ; Wilson James W.. Semiconductor structure interconnector and assembly. USP2000056059579.
  10. Buck Roy V.. Stress relief substrate for solder ball grid array mounted circuits and method of packaging. USP2000126163462.

이 특허를 인용한 특허 피인용횟수: 56

  1. Leedy, Glenn J. Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer. USP2011108035233.
  2. Ebefors, Thorbjorn; Perttu, Daniel. CTE matched interposer and method of making. USP2015129224681.
  3. Cooney, Robert C.; Wilkinson, Joseph M.. Circuit board with an attached die and intermediate interposer. USP2011077982137.
  4. Chiu,Anthony M.; Tee,Tong Yan. Copper interposer for reducing warping of integrated circuit packages and method of making IC packages. USP2007037196425.
  5. Shah, Sharad M.; Bach, David R.; Villani, Angelo; Palmer, Nicholas. Dual interposer packaging for high density interconnect. USP2004116812485.
  6. Hu, Yen-Chang; Huang, Chang-Chia; Hsiao, Ching-Wen; Chen, Chen-Shien. Fan-out package comprising bulk metal. USP2014108866285.
  7. Gamand, Patrice; Yannou, Jean-Marc; Verjus, Fabrice; Cathelin, Cyrille. Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip. USP2012058178901.
  8. Saiki,Hajime; Urashima,Kazuhiro. Intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, and structure having semiconductor element, intermediate substrate and substrate. USP2008017317165.
  9. Sundstrom,Lance L.. Interposer for compliant interfacial coupling. USP2008127462939.
  10. Conn, Robert O.. Interposer for redistributing signals. USP2011118062968.
  11. Pearson, Thomas E.; Arrigotti, George L.; Aspandiar, Raiyomand F.; Combs, Christopher D.. Interposer to couple a microelectronic device package to a circuit board. USP2004096791035.
  12. Conn, Robert O.. Interposing structure. USP2009077566960.
  13. Voraberger, Hannes; Schmid, Gerhard; Riester, Markus; Stahr, Johannes. Method for fixing an electronic component on a printed circuit board and system comprising a printed circuit board and at least one electronic component. USP2013098541690.
  14. Cooney, Robert C.; Wilkinson, Joseph M.. Method of attaching die to circuit board with an intermediate interposer. USP2013078481861.
  15. Hu, Shou-Cheng; Chen, Chen-Shien; Kuo, Tin-Hao; Chen, Chih-Hua; Hsiao, Ching-Wen. Methods and apparatus for package on package devices with reversed stud bump through via interconnections. USP2016039293449.
  16. Hu, Yen-Chang; Hsiao, Ching-Wen; Chen, Chih-Hua; Chen, Chen-Shien; Kuo, Tin-Hao. Methods and apparatus for package on package devices with reversed stud bump through via interconnections. USP2014128922005.
  17. Lian, Jia; Peng, Huaping; Shi, Shamei; Wang, William H; Flens, Frank; Vergeest, Henricus Jozef. Module mount interposer. USP20190210218098.
  18. Brodsky, William Louis; Chan, Benson; Gaynes, Michael Anthony; Markovich, Voya Rista. Printed wiring board interposer sub-assembly. USP2003046545226.
  19. Kawano,Masaya. Semiconductor device. USP2007077247935.
  20. Kawano,Masaya. Semiconductor device. USP2008077405472.
  21. Shinagawa, Masatoshi. Semiconductor device. USP2010087768138.
  22. Yap, Weng Foong. Semiconductor device package and methods of manufacture thereof. USP2017109786515.
  23. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko. Semiconductor memory device and manufacturing method thereof. USP2009087576433.
  24. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko. Semiconductor memory device and manufacturing method thereof. USP2012108298940.
  25. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko. Semiconductor memory device and manufacturing method thereof. USP2011027893540.
  26. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko. Semiconductor memory device and manufacturing method thereof. USP2013088513121.
  27. Lee, Woong Sun; Chung, Qwan Ho; Cho, Il Hwan; Lim, Sang Joon; Yoo, Jong Woo; Bae, Jin Ho; Lee, Seung Hyun. Semiconductor package having substrate for high speed semiconductor package. USP2013058441116.
  28. Kim, Jong-Kook; Jang, Byoung-Wook. Semiconductor package stack structure having interposer substrate. USP2016059349713.
  29. Fritz, Donald S.. Semiconductor package with stress inhibiting intermediate mounting substrate. USP2004056734540.
  30. Spielberger, Richard K.; Jensen, Ronald J.; Wagner, Thomas G.. Stacked ball grid array. USP2003126657134.
  31. Wong, Tse E.; Tonomura, Samuel D.; Sox, Stephen E.; Dearden, Timothy E.; Quan, Clifton; Chan, Polwin C.; Hauhe, Mark S.. Stacked integrated circuit assembly. USP2009107605477.
  32. Wong, Tse E.; Tonomura, Samuel D.; Sox, Stephen E.; Dearden, Timothy E.; Quan, Clifton; Chan, Polwin C.; Hauhe, Mark S.. Stacked integrated circuit assembly. USP2011027888176.
  33. Leedy, Glenn J.. Stacked integrated memory device. USP2016079401183.
  34. Ye, Seng Kim Dalson; Chong, Chin Hui; Lee, Choon Kuan; Lee, Wang Lai; Said, Roslan Bin. Stacked microelectronic devices. USP2017059640458.
  35. Yu, Chen-Hua; Wu, Jiun Yi. Substrate contact opening. USP2016039275964.
  36. Yu, Chen-Hua; Wu, Jiun Yi. Substrate contact opening. USP2014048698306.
  37. Xing, Andrew. System and method for mounting a stack-up structure. USP2003026519157.
  38. Hughes, John A.; Love, Thomas E.; Lemoine, Eugene; Lee, David H.; Ebel, Christopher. System and method for multi-chip module die extraction and replacement. USP2012128338230.
  39. Hughes, John A.; Love, Thomas E.; Lemoine, Eugene; Lee, David H.; Ebel, Christopher. System and method for multi-chip module die extraction and replacement. USP2011118067829.
  40. Sundstrom,Lance L.. System and method of attaching an integrated circuit assembly to a printed wiring board. USP2009017476570.
  41. Bolken, Todd O.; Cobbley, Chad A.. Techniques for packaging a multiple device component. USP2010097804171.
  42. Leedy, Glenn J. Three dimension structure memory. USP2015079087556.
  43. Leedy, Glenn J. Three dimensional memory structure. USP2014098841778.
  44. Leedy, Glenn J. Three dimensional memory structure. USP2014088796862.
  45. Leedy, Glenn J. Three dimensional structure memory. USP2014078791581.
  46. Leedy, Glenn J. Three dimensional structure memory. USP2014128907499.
  47. Leedy, Glenn J. Three dimensional structure memory. USP2014028653672.
  48. Leedy, Glenn J.. Three dimensional structure memory. USP2013048410617.
  49. Leedy, Glenn J.. Three dimensional structure memory. USP2012108288206.
  50. Leedy, Glenn J.. Three dimensional structure memory. USP2015018933570.
  51. Leedy, Glenn J.. Three dimensional structure memory. USP2012118318538.
  52. Leedy, Glenn J.. Three dimensional structure memory. USP2014018629542.
  53. Leedy, Glenn J.. Three dimensional structure memory. USP2015018928119.
  54. Leedy, Glenn J.. Three dimensional structure memory. USP2014098824159.
  55. Leedy, Glenn J. Vertical system integration. USP2013118587102.
  56. Leedy, Glenn J. Vertical system integration. USP2012098269327.

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