초록 ▼

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization b

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

대표청구항 ▼

1. A structure comprising:a layer of dielectric on a substrate, at least one trench formed in said dielectric on said substrate, a metal liner formed in said trench, a conductor selected from the group consisting of copper and copper alloys on said liner filling said trench, a planarized upper surfa

1. A structure comprising:a layer of dielectric on a substrate, at least one trench formed in said dielectric on said substrate, a metal liner formed in said trench, a conductor selected from the group consisting of copper and copper alloys on said liner filling said trench, a planarized upper surface of said conductor with the upper surface of said layer of dielectric, and a conductive film over said upper surface of said conductor only, said conductive film having a thickness in the range from 1 to 20 nm and forming a metal to metal chemical and metallurgical bond to provide high electromigration resistance and high resistance to thermal stress voiding and whereby said upper surface of said conductor and said upper surface of said layer of dielectric remain within 20 nm of being co-planar, said conductive film selected from the group consisting of CoWP, CoSnP, CoP, CoB, CoSnB, CoWB and In whereby said upper surface of said conductor is protected from oxidation and corrosion.