초록 ▼

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

대표청구항 ▼

1. A method for organizing 2M single-bit memory cells into 2N blocks, where M is a multiplication-product of N by I by J, and N, I and J are positive integers, the method comprising steps of:(a) dividing said 2M single-bit memory cells into N pairs with each pair includes two symmetrical blocks wher

1. A method for organizing 2M single-bit memory cells into 2N blocks, where M is a multiplication-product of N by I by J, and N, I and J are positive integers, the method comprising steps of:(a) dividing said 2M single-bit memory cells into N pairs with each pair includes two symmetrical blocks where each of said block includes {J(j).times.I} single-bit memory cells, and where j=1, 2, 3, . . . , N, and said positive integer I representing a bit length of a stored data; (b) arranging said single-bit memory cells in each of said blocks into a J(j)-by-I two dimensional array and by connecting every I single memory cells with a first level bit line in a first bit-line direction and every J(j) single-memory cells by a first level word line wherein each said first level word lines and said first level bit lines intersect at one of said single-bit memory cells; (c) connecting each of said I first level bit lines in each of said blocks to a corresponding multiple-block first level bit-lines, i.e., multiple-block bit-line-i where i=1, 2, 3, . . . I, wherein said multiple-block first-level bit lines being arranged in a second bit-line direction different from said first-bit line direction and each being connected to a corresponding first level sense-amplifier-i where i=1, 2, 3, . . . I; (d) applying a block select signal to activate one of said J(j) first level word lines in one of said blocks, i.e., block-n where n is a positive integer ranging from 1 to N, and employing said I sense amplifiers for detecting memory-cell signals from each of said first level I bit lines of said block n and a corresponding symmetrical block of said block-n, for reading data therefrom whereby said N blocks sharing said I sense amplifiers; and (e) forming a select transistor for each of said memory cells for connecting to one of said first level word lines and applying a bias voltage on a gate of said select transistor for blocking a leakage current flowing through a channel controlled by said gate when said select transistor is in a standby mode.