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Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
출원번호 US-0589818 (2000-06-07)
발명자 / 주소
  • Lawrence A. Clevenger
  • Louis L. C. Hsu
  • Jeremy K. Stephens
  • Michael Wise
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    DeLio & Peterson, LLC
인용정보 피인용 횟수 : 11  인용 특허 : 17

초록

A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A

대표청구항

1. A method of planarizing a semiconductor comprising:forming a first layer of a first material comprising a diamond-like carbon material on a surface of a substrate, said first layer comprising a first polish stop; forming a second layer of a second material on the surface of said first layer, said

이 특허에 인용된 특허 (17)

  1. Jaso Mark A. (Yorktown Heights NY) Jones Paul B. (Wappingers Falls NY) Meyerson Bernard S. (Yorktown Heights NY) Patel Vishnubhai V. (Yorktown Heights NY), CVD diamond or diamond-like carbon for chemical-mechanical polish etch stop.
  2. Grill Alfred ; Hummel John Patrick ; Jahnes Christopher Vincent ; Patel Vishnubhai Vitthalbhai ; Saenger Katherine Lynn, Dual damascene processing for semiconductor chip interconnects.
  3. Somekh Sasson, Etch stop layer for dual damascene process.
  4. Arnold Norbert, Integrated circuit devices including shallow trench isolation.
  5. Joyner Keith A., Method for forming an isolation structure in a substrate.
  6. Geffken Robert M. ; Luce Stephen E., Method of forming a self-aligned copper diffusion barrier in vias.
  7. Chow Ming-Fea (Poughquagh NY) Guthrie William L. (Hopewell Junction NY) Kaufman Frank B. (Amawalk NY), Method of forming fine conductive lines, patterns and connectors.
  8. Chan Lap ; Cha Cher Liang,SGX ; Lee Teck Koon,SGX, Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing.
  9. Oh Yong-Chul,KRX, Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids.
  10. Beilin Solomon I. ; Lee Michael G. ; Chou William T. ; Moresco Larry Louis ; Wang Wen-chou Vincent, Methods of planarizing structures on wafers and substrates by polishing.
  11. Jang S. M.,TWX ; Yu C. H.,TWX, Planarization of shallow trench isolation by differential etchback and chemical mechanical polishing.
  12. Ronay Maria, Polish process and slurry for planarization.
  13. Perry Jeff ; Bergemont Albert, Process for fabricating trench isolation structure for integrated circuits.
  14. Jang S. M.,TWX ; Chen Y. H.,TWX ; Yu C. H.,TWX, Self-planarized gapfilling for shallow trench isolation.
  15. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.
  16. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
  17. Gardner Donald S. (Mountain View CA), Wetting layer sidewalls to promote copper reflow into grooves.

이 특허를 인용한 특허 (11)

  1. Chen, Yanfeng; Tang, Yunjun; Qian, Yana; Yang, Ming M.; Li, Yunfei; Anderson, Paul E., Damascene process using PVD sputter carbon film as CMP stop layer for forming a magnetic recording head.
  2. Huang,Picheng; Anderson,Paul E.; Stearns,Laura C.; Xue,Song S., Magnetic devices having magnetic features with CMP stop layers.
  3. Biskeborn, Robert G.; Lo, Calvin S.; Decad, Gary M.; Hwang, Cherngye, Magnetic recording head coating and method.
  4. Daamen, Roel; Nguyen Hoang, Viet; Hoofman, Romano Julma Oscar Maria; Verheijden, Greja Johanna Adriana Maria, Method for fabrication of in-laid metal interconnects.
  5. Kim,Dong Chan; Kang,Chang Jin; Chi,Kyeong Koo; Chung,Sung Hoon, Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks.
  6. Jin, Michael S.; Lee, Sing H.; Reynolds, James A., Phase-shift masks and methods of fabrication.
  7. Lim, Sin Leng; Kim, In Ki; Park, Jong Sung; Kim, Min Hwan; Lu, Wei, Planarized passivation layer for semiconductor devices.
  8. Lim, Sin Leng; Kim, In Ki; Park, Jong Sung; Kim, Min Hwan; Lu, Wei, Planarized passivation layer for semiconductor devices.
  9. Drummer,Heike; Kreupl,Franz; S채nger,Annette; Engelhardt,Manfred; Sell,Bernhard; Thieme,Peter, Process for producing and removing a mask layer.
  10. Desai, Mukesh; Moeggenborg, Kevin; Carter, Phillip, Silicon carbide polishing method utilizing water-soluble oxidizers.
  11. White, Michael L.; Jones, Lamon; Gilliland, Jeffrey; Moeggenborg, Kevin, Silicon carbide polishing method utilizing water-soluble oxidizers.
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