초록 ▼

In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to t

In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

대표청구항 ▼

1. A thin film magnetic memory device, comprising:a memory array including a plurality of magnetic memory cells arranged in rows and columns, each of said plurality of magnetic memory cells having either a first or second resistance value according a storage data level thereof; a plurality of first

1. A thin film magnetic memory device, comprising:a memory array including a plurality of magnetic memory cells arranged in rows and columns, each of said plurality of magnetic memory cells having either a first or second resistance value according a storage data level thereof; a plurality of first bit lines provided corresponding to the respective columns of the magnetic memory cells; a plurality of read word lines provided corresponding to the respective rows of the magnetic memory cells, for electrically coupling the magnetic memory cells corresponding to an addressed row between said plurality of first bit lines each being set to a first voltage and a second voltage so as to pass a data read current through the magnetic memory cells; a first read data line for transmitting read data; a read gate circuit for setting a voltage of said first read data line according to a voltage on one of said plurality of first bit lines that corresponds to an addressed column; and a data read circuit for setting a level of the read data according to the voltage on the first read data line.