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Method of improving pad metal adhesion

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/4763
출원번호 US-0431152 (1999-11-01)
발명자 / 주소
  • Sheng-Hsiung Chen TW
  • Fan Keng Yang TW
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company TW
대리인 / 주소
    George O. Saile
인용정보 피인용 횟수 : 20  인용 특허 : 8

초록

The present invention is a new and improved method for fabricating aluminum metal pad structures wherein a thin adhesion layer of aluminum is placed in between the underlying copper metal and the top tantalum nitride pad barrier layer providing improved adhesion to the pad metal stack structure. In

대표청구항

1. A method of fabricating multi-level interconnects in an integrated circuit and other devices on a substrate, the method comprising the steps of:(a) providing a substrate or a module; (b) providing said substrate with a layer of an interlevel dielectric over the substrate; (c) providing a first le

이 특허에 인용된 특허 (8)

  1. Cheung Robin W. ; Lin Ming-Ren, Advanced copper interconnect system that is compatible with existing IC wire bonding technology.
  2. Hong Qi-Zhong (Dallas TX) Jeng Shin-Puu (Plano TX) Havemann Robert H. (Garland TX), Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits.
  3. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  4. Kim Jun K. (Seoul KRX) Lee Kyung I. (Seoul KRX), Method for forming a copper metal wiring with aluminum containing oxidation barrier.
  5. Kim Do Heyoung,KRX, Method of fabricating metal line structure.
  6. Chan Lap ; Yap Kuan Pei,MYX ; Tee Kheng Chok,MYX ; Ip Flora S.,SGX ; Loh Wye Boon,MYX, Passivation of copper interconnect surfaces with a passivating metal layer.
  7. Anschel Morris (Wappingers Falls NY) Ormond Douglas W. (Wappingers Falls NY) Hayunga Carl P. (Poughkeepsie NY), Thin film metallization process for improved metal to substrate adhesion.
  8. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (20)

  1. Huang, Tai-Chun; Yao, Chih-Hsiang; Wan, Wen-Kai, Bond pad structure with stress-buffering layer capping interconnection metal layer.
  2. Shih, Chien Hsueh; Tsai, Minghsing; Su, Hung Wen; Shue, Shau Lin, Copper interconnection with conductive polymer layer and method of forming the same.
  3. Wang, Xinpeng; Zhang, Chenglong; Huang, Ruixuan, Device having reduced pad peeling during tensile stress testing and a method of forming thereof.
  4. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  5. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  6. Lewandowski, Eric P.; Nah, Jae-Woong; Sorce, Peter J., Method for forming solder bumps using sacrificial layer.
  7. Burrell,Lloyd G.; Davis,Charles R.; Goldblatt,Ronald D.; Landers,William F.; Mehta,Sanjay C., Method of fabricating a wire bond pad with Ni/Au metallization.
  8. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  9. Hatano, Masaaki; Usui, Takamasa, Semiconductor device.
  10. Hatano,Keisuke; Abiru,Takahisa, Semiconductor device.
  11. Tanaka, Takekazu; Takahashi, Kouhei; Okabe, Seiji, Semiconductor device.
  12. Chen, Chun-Liang, Semiconductor device allowing metal layer routing formed directly under metal pad.
  13. Chen, Chun-Liang, Semiconductor device allowing metal layer routing formed directly under metal pad.
  14. Chen, Chun-Liang; Chang, Tien-Chang; Lin, Chien-Chih, Semiconductor device allowing metal layer routing formed directly under metal pad.
  15. Chen, Chun-Liang; Chang, Tien-Chang; Lin, Chien-Chih, Semiconductor device allowing metal layer routing formed directly under metal pad.
  16. Chen, Chun-Liang; Chang, Tien-Chang; Lin, Chien-Chih, Semiconductor device allowing metal layer routing formed directly under metal pad.
  17. Burrell, Lloyd G.; Wong, Kwong H.; Kelly, Adreanne A.; McKnight, Samuel R., Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad.
  18. Tanaka, Takekazu; Takahashi, Kouhei; Okabe, Seiji, Semiconductor device including a coupling region which includes layers of aluminum and copper alloys.
  19. Tanaka, Takekazu; Takahashi, Kouhei; Okabe, Seiji, Semiconductor device including coupling ball with layers of aluminum and copper alloys.
  20. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
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