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A semiconductor module has a plurality of power semiconductor devices mounted on a substrate, and a metal foil for wiring is mounted on the substrate so that an asymmetric unit arrangement of the semiconductor devices is formed. In the device, all of the units are arranged in the same direction on t

A semiconductor module has a plurality of power semiconductor devices mounted on a substrate, and a metal foil for wiring is mounted on the substrate so that an asymmetric unit arrangement of the semiconductor devices is formed. In the device, all of the units are arranged in the same direction on the substrate, and all of the units are electrically connected with electrode terminal feet, and the electrode terminal feet are electrically connected with linkage terminal foot. The electrode terminal feet are disposed with a certain interval.

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1. A semiconductor module comprising:a metal substrate; a plurality of insulating substrates mounted on said metal substrate; power semiconductor devices, wherein an equal plural number of power semiconductor devices are mounted on each of said insulating substrates; and metal conductors for wiring,

1. A semiconductor module comprising:a metal substrate; a plurality of insulating substrates mounted on said metal substrate; power semiconductor devices, wherein an equal plural number of power semiconductor devices are mounted on each of said insulating substrates; and metal conductors for wiring, wherein an equal plural number of metal conductors are mounted on each of said insulating substrates, wherein said insulating substrates are arranged in substantially a same direction forming a row of insulating substrates on said metal substrate, wherein said metal conductors are electrically connected with electrode terminal feet, said electrode terminal feet being electrically connected with a linkage terminal foot and being disposed with a certain interval therebetween, respectively, wherein said power semiconductor devices and said metal conductors are disposed in a substantially same and asymmetrical arrangement, with respect to a plan view layout, on each of said insulating substrates, respectively, and wherein the interval between the electrode terminal feet of adjacent insulating substrates in said row of insulating substrates is substantially equal to the interval between corresponding semiconductor devices, which are similarly positioned, on each of the adjacent insulating substrates, respectively.