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Thermally enhanced packaged semiconductor assemblies 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B23K-031/02
출원번호 US-0385324 (1999-08-30)
발명자 / 주소
  • Thomas H. Distefano
출원인 / 주소
  • Tessera, Inc.
대리인 / 주소
    Lerner, David, Littenberg, Krumholz & Mentlik, LLP
인용정보 피인용 횟수 : 22  인용 특허 : 38

초록

A thermally enhanced semiconductor package includes a sheet metal cap having flexible flanges provided with solder contacts for reliable attachment to a circuit board. The package assembly further includes a semiconductor chip with a contact-bearing front surface facing forwardly, and chip bonding c

대표청구항

1. A method of making a plurality of chip assemblies comprising:(a) providing a metallic element having one or more rear regions and one or more flange regions offset from said rear regions in a forward direction; (b) placing a plurality of semiconductor chips into said one or more rear regions in f

이 특허에 인용된 특허 (38)

  1. Adler Stanford L. (Warwick NY) Campisi John (Riverside CT) Leong Koon-Wah (Ossining NY), Analytical test device and the use thereof.
  2. Banerji Kingshuk (Plantation FL) Nounou Fadia (Plantation FL) Mullen ; III William B. (Boca Raton FL), Backplane grounding for flip-chip integrated circuit.
  3. Hoffman Paul R., Ball grid array electronic package standoff design.
  4. Neugebauer Constantine A. (Schenectady NY) Temple Victor A. K. (Jonesville NY), Batch assembly of high density hermetic packages for power semiconductor chips.
  5. Dalal Hormazdyar M. ; Gaudenzi Gene Joseph ; Gorrell Rebecca Y. ; Takacs Mark A. ; Travis ; Jr. Kenneth J., Capacitor with multi-level interconnection technology.
  6. Covell ; II James H. ; Bolde Lannie R. ; Edwards David L. ; Goldmann Lewis S. ; Gruber Peter A. ; Toy Hilton T., Cast metal seal for semiconductor substrates and process thereof.
  7. Degani Yinon (Highland Park NJ) Dudderar Thomas D. (Chatham NJ) Han Byung J. (Scotch Plains NJ) Raju Venkataram R. (New Providence NJ), Electronic device package having electronic device boonded, at a localized region thereof, to circuit board.
  8. Andros Frank Edward ; Bupp James Russell ; DiPietro Michael ; Hammer Richard Benjamin, Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device.
  9. Bearinger Clayton R. (Midland MI) Camilletti Robert C. (Midland MI) Kilby Jack S. (Dallas TX) Haluska Loren A. (Midland MI) Michael Keith W. (Midland MI), Flip chip silicone pressure sensitive conductive adhesive.
  10. Berndlmaier Erich (Wappingers Falls NY) Clark Bernard T. (Poughquag NY) Dorler Jack A. (Wappingers Falls NY), Heat transfer structure for integrated circuit package.
  11. Temple Victor A. K. (Clifton NY) Glascock ; II Homer H. (Millis MA), Hermetic package for a high power semiconductor device.
  12. Schulman Joseph H. ; Canfield Lyle Dean, Hermetically sealed electrical feedthrough for use with implantable electronic devices.
  13. Costigan Jack P. (Mountaintop PA), Hermetically sealed housing with welding seal.
  14. Ross Richard J. (Moraga CA), Integrated circuit packages with heat dissipation for high current load.
  15. Blair Kelvin R. (Tempe AZ) Furman Lynn C. (Tempe AZ) Knott David M. (Scottsdale AZ), Low-cost power device package with quick-connect terminals and electrically isolated mounting means.
  16. Sherif Raed A. ; Courtney Mark Gerard ; Edwards David Linn ; Fahey Albert Joseph ; Hopper Gregory Scott ; Iruvanti Sushumna ; Jones Charles Frederick ; Messina Gaetano Paolo, Method and apparatus for cooling of chips using a plurality of customized thermally conductive materials.
  17. Abe Yoshinari (Kawasaki JPX), Method and device for managing programs.
  18. Braden Jeffrey S. (Milpitas CA), Method for housing a tape-bonded electronic device and the package employed.
  19. Ross Richard J., Method of assembling integrated circuit package.
  20. Temple Victor A. K. (Clifton NY) Glascock ; II Homer H. (Millis MA), Method of packaging a semiconductor device.
  21. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA), Microelectronic mounting with multiple lead deformation and bonding.
  22. Hoffman Louis S. (Morristown NJ), Package having sealed closing means.
  23. Bhattacharyya Bidyut K. (Chandler AZ) Wilson J. D. (Phoenix AZ), Power distribution lid for IC package.
  24. Hoffman Louis S. (Morristown NJ) Kurlander Susan L. (Hoboken NJ), Sealed moistureproof container.
  25. Gross Larry D. ; Cadovius Richard W.,CAX, Semiconductor cap.
  26. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies having interposer and flexible lead.
  27. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with fan-in leads.
  28. DiStefano, Thomas H.; Grube, Gary W.; Khandros, Igor Y.; Mathiew, Gaetan, Semiconductor connection components and method with releasable lead support.
  29. Tanaka Masato (Nakano JPX) Fukase Katsuya (Nagano JPX) Shimizu Mitsuharu (Nagano JPX) Murakami Toshiyuki (Nagano JPX), Semiconductor device and lead frame used therein.
  30. Knapp James H. (Chandler AZ) Nelson Keith E. (Tempe AZ), Semiconductor device package and method of making.
  31. Kobayashi Kenzi (Tokyo JPX) Mori Hajime (Tokyo JPX) Yamaguti Yukio (Tokyo JPX), Semiconductor device package having locating mechanism for properly positioning semiconductor device within package.
  32. Hosomi Eiichi,JPX ; Tazawa Hiroshi,JPX ; Takubo Chiaki,JPX ; Shibasaki Koji,JPX, Semiconductor device, method of fabricating the same and copper leads.
  33. Temple Victor A. K. (Clifton Park NY), Semiconductor devices and methods of assembly thereof.
  34. Tachibana Hirofumi,JPX, Semiconductor package and method of manufacturing the same.
  35. Arima Hideo (Yokohama JPX) Matsui Kiyoshi (Yokohama JPX) Takeda Kenji (Kamakura JPX), Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositel.
  36. Balderes Demetrios (Wappingers Falls NY) Lynch John R. (Hopewell Junction NY) Yacavonis Robert A. (Poughkeepsie NY), Semiconductor package with improved conduction cooling structure.
  37. Miura Shinya (Hadano JPX) Kanda Kouzou (Hadano JPX) Shirai Mitsugu (Hadano JPX), Semiconductor package with metalized portions.
  38. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Thin, molded, surface mount electronic device.

이 특허를 인용한 특허 (22)

  1. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
  2. Hirano, Koichi; Nakatani, Seiichi; Handa, Hiroyuki; Yoshida, Tsunenori; Yamashita, Yoshihisa; Ishitomi, Hiroyuki, Circuit component, circuit component package, circuit component built-in module, circuit component package production and circuit component built-in module production.
  3. Saita, Hitoshi; Horino, Kenji; Oikawa, Yasunobu; Kakei, Shinichiro, Electronic component and electronic component module.
  4. Siu, Paul, Hermetically sealed component assembly package.
  5. Dosdos, S. Gabriel R.; Kim, Dong Wook, Integrated circuit package and method of forming an integrated circuit package.
  6. Zohni, Nael; Nagarajan, Kumar; Boja, Ronilo, Integrated circuit packaging devices and methods.
  7. Mangrum,Marc A., Method for stacking an integrated circuit on another integrated circuit.
  8. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
  9. Hirano,Koichi; Nakatani,Seiichi; Handa,Hiroyuki; Yoshida,Tsunenori; Yamashita,Yoshihisa; Ishitomi,Hiroyuki, Method of producing circuit component built-in module with embedded circuit component.
  10. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  11. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  12. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  13. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  14. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  15. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  16. Haba, Belgacem; McElrea, Simon, Microelectronic assembly with thermally and electrically conductive underfill.
  17. Lin, Mou-Shiung; Peng, Bryan, Multiple chips bonded to packaging structure with low noise and multiple selectable functions.
  18. Na, Young-Mi; Kim, Min-Gu, Probe card, thermal insulation cover assembly for probe card, and semiconductor device test apparatus including the same.
  19. Lin, Mou-Shiung; Chou, Chiu-Ming, Semiconductor chip and method for fabricating the same.
  20. Shivkumar, Bharat; Cheah, Chuan, Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance.
  21. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  22. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
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