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An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow executi

An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an "XV" instruction for "eXecute VLIW", or LV for "Load VLIW"). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses. These addressing techniques provide tremendous flexibility for VLIW instruction execution.

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1. An apparatus including a plurality of addressing modes for providing indirect access to very long instruction words (VLIWs) allowing both sequential code and parallel operations in the form of VLIWs to be encoded efficiently, wherein the sequential code comprising a sequence of short instruction

1. An apparatus including a plurality of addressing modes for providing indirect access to very long instruction words (VLIWs) allowing both sequential code and parallel operations in the form of VLIWs to be encoded efficiently, wherein the sequential code comprising a sequence of short instruction words (SIWs) including indirect VLIW SIWs is loaded as part of a single instruction stream, the apparatus comprising:a short instruction memory fetch logic for fetching a short instruction word from a short instruction memory (SIM); the short instruction memory storing the short instruction word, said short instruction word including a field defining an addressing mode associated with the short instruction word, wherein said addressing mode is one of the plurality of addressing modes for accessing the VLIW instruction; an instruction decoder for decoding the short instruction word; a VLIW instruction memory (VIM) for storing VLIW instructions; a VLIW memory address unit (VIM AGU) for determining the addressing mode associated with the short instruction word; VIM address registers; and a VIM address generation mechanism for selecting a VLIW in said VIM by generating a VIM address according to the address mode associated with said short instruction word; wherein said addressing mode associated with the short instruction word is one of said plurality of addressing modes: a direct VIM addressing mode, a base plus offset addressing mode, an indirect/indexed addressing mode, a circular indexed addressing mode, or a processing element (PE) relative addressing mode.