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Method of forming barrier layers for damascene interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0641834 (2000-08-18)
발명자 / 주소
  • Daniel C. Edelstein
  • Timothy J. Dalton
  • John G. Gaudiello
  • Mahadevaiyer Krishnan
  • Sandra G. Malhotra
  • Maurice McGlashan-Powell
  • Eugene J. O'Sullivan
  • Carlos J. Sambucetti
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Ratner & Prestia
인용정보 피인용 횟수 : 61  인용 특허 : 15

초록

A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mech

대표청구항

1. A method comprising the steps of:(A) depositing a dielectric layer on a substrate; (B) depositing a chemical mechanical polish-stop layer on the dielectric layer; (C) forming an opening through the chemical mechanical polish-stop layer and at least partially in the dielectric layer; (D) depositin

이 특허에 인용된 특허 (15)

  1. Chan Lap ; Zheng Jia Zhen,SGX, Barrier layer.
  2. Beyer Klaus D. (Poughkeepsie NY) Guthrie William L. (Poughkeepsie NY) Makarewicz Stanley R. (New Windsor NY) Mendel Eric (Poughkeepsie NY) Patrick William J. (Newburgh NY) Perry Kathleen A. (Lagrange, Chem-mech polishing method for producing coplanar metal/insulator films on a substrate.
  3. Bai Gang ; Fraser David B., Diffusion barrier for electrical interconnects in an integrated circuit.
  4. Licata Thomas John ; Nunes Ronald Wayne ; Okazaki Motoya, Dual damascene process having tapered vias.
  5. Filipiak Stanley M. (Pflugerville TX) Gelatos Avgerinos (Austin TX), Method for capping copper in semiconductor devices.
  6. Roy Sudipto Ranendra,SGX, Method for forming copper damascene structures by using a dual CMP barrier layer.
  7. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  8. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  9. Matsunaga Noriaki,JPX ; Shibata Hideki,JPX ; Matsuno Tadashi,JPX ; Usui Takamasa, Method of forming semiconductor device having an improved buried electrode formed by selective CVD.
  10. Zhao Bin, Method of making a damascene metallization.
  11. Hoshino Kazuhiro (Tokyo JPX), Method of producing semiconductor device.
  12. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  13. Landers William Francis (Beacon NY) Rutten Matthew Jeremy (Milton VT) Fisher ; Jr. Thomas Robert (Beacon NY) Schaffer Dean Allen (South Burlington VT), Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride.
  14. Jeng Shin-Puu, Semiconductor device having damascene interconnects.
  15. Jang Syun-Ming,TWX, Use of stop layer for chemical mechanical polishing of CU damascene.

이 특허를 인용한 특허 (61)

  1. Shin, Dong-Mok; Choi, Eun-Mi; Cho, Seung-Beom; Ha, Hyun-Chul, CMP slurry composition for forming metal wiring line.
  2. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  3. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  4. Yang, Chih-Chao; Bergendahl, Marc A.; Horak, David V.; Li, Baozhen; Ponoth, Shom, Copper interconnect structures and methods of making same.
  5. Yang, Chih-Chao; Bergendahl, Marc A.; Horak, David V.; Li, Baozhen; Ponoth, Shom, Copper interconnect structures and methods of making same.
  6. Smith, Joseph; Howard, Emmett; Blain Christen, Jennifer, Deformable electronic device and methods of providing and using deformable electronic device.
  7. Edelstein, Daniel C.; Colburn, Matthew E.; Cooney, III, Edward C.; Dalton, Timothy J.; Fitzsimmons, John A.; Gambino, Jeffrey P.; Huang, Elbert E.; Lane, Michael W.; McGahay, Vincent J.; Nicholson, Lee M.; Nitta, Satyanarayana V.; Purushothaman, Sampath; Sankaran, Sujatha; Shaw, Thomas M.; Simon, Andrew H.; Stamper, Anthony K., Device and methodology for reducing effective dielectric constant in semiconductor devices.
  8. Edelstein, Daniel C.; Colburn, Matthew E.; Cooney, III, Edward C.; Dalton, Timothy J.; Fitzsimmons, John A.; Gambino, Jeffrey P.; Huang, Elbert E.; Lane, Michael W.; McGahay, Vincent J.; Nicholson, Lee M.; Nitta, Satyanarayana V.; Purushothaman, Sampath; Sankaran, Sujatha; Shaw, Thomas M.; Simon, Andrew H.; Stamper, Anthony K., Device and methodology for reducing effective dielectric constant in semiconductor devices.
  9. Wu, Yung-Hsu; Lu, Hsin-Hsien; Bao, Tien-I; Shue, Shau-Lin, Dielectric protection layer as a chemical-mechanical polishing stop layer.
  10. Marrs, Michael, Dual active layer semiconductor device and method of manufacturing the same.
  11. Smith, Joseph T.; Marrs, Michael, Dual active layer semiconductor device and method of manufacturing the same.
  12. Smith, Joseph; Howard, Emmett; Blain Christen, Jennifer; Lee, Yong-Kyun, Electronic device and methods of providing and using electronic device.
  13. Chiras, Stefanie Ruth; Lane, Michael Wayne; Malhotra, Sandra Guy; Mc Feely, Fenton Reed; Rosenberg, Robert; Sambucetti, Carlos Juan; Vereecken, Philippe Mark, Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures.
  14. Dalton,Timothy J; Gates,Stephen M, Formation of low resistance via contacts in interconnect structures.
  15. Furman, Bruce Kenneth; Surendra, Maheswaran; Goma, Sherif A.; Karecki, Simon M.; Karecki, Anna; Magerlein, John Harold; Petrarca, Kevin Shawn; Purushothaman, Sampath; Sambucetti, Carlos Juan; Volant,, High density raised stud microjoining system and methods of fabricating the same.
  16. Xu, Xingling; Webb, Eric, High speed copper plating bath.
  17. Farrar, Paul A., Integrated circuit insulators and related methods.
  18. Farrar, Paul A., Integrated circuit insulators and related methods.
  19. Weng, Cheng-Hui; Lin, Chun-Chieh; Su, Hung-Wen, Integrated circuit structure and formation.
  20. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Interconnect structures and a method of electroless introduction of interconnect structures.
  21. Dubin, Valery M.; Cheng, Chin-Chang; Hussein, Makarem; Nguyen, Phi L.; Brain, Ruth A., Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs.
  22. He, Jun; Fischer, Kevin J.; Zhou, Ying; Moon, Peter K., Interconnects having sealing structures to enable selective metal capping layers.
  23. He, Jun; Fischer, Kevin J.; Zhou, Ying; Moon, Peter K., Interconnects having sealing structures to enable selective metal capping layers.
  24. He, Jun; Fischer, Kevin J.; Zhou, Ying; Moon, Peter K., Interconnects having sealing structures to enable selective metal capping layers.
  25. He, Jun; Fischer, Kevin J.; Zhou, Ying; Moon, Peter K., Interconnects having sealing structures to enable selective metal capping layers.
  26. Amanapu, Hari P.; Peethala, Cornelius Brown; Patlolla, Raghuveer R.; Yang, Chih-Chao; Nogami, Takeshi, Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers.
  27. Bonilla, Griselda; Chen, Shyng-Tsong; Colburn, Matthew E.; Yang, Chih-Chao, Metal capping process for BEOL interconnect with air gaps.
  28. Daubenspeck, Timothy H.; Landers, William F.; Zupanski-Nielsen, Donna S., Method for fabricating last level copper-to-C4 connection with interfacial cap structure.
  29. Goldberg, Cindy K.; Filipiak, Stanley Michael; Flake, John C.; Lii, Yeong-Jyh T.; Smith, Bradley P.; Solomentsev, Yuri E.; Sparks, Terry G.; Strozewski, Kirk J.; Yu, Kathleen C., Method for forming a passivation layer for air gap formation.
  30. McGlashan-Powell, Maurice; O'Sullivan, Eugene J.; Edelstein, Daniel C., Method for forming an indium cap layer.
  31. McGlashan-Powell, Maurice; O'Sullivan, Eugene J.; Edelstein, Daniel C., Method for forming an indium cap layer.
  32. Angyal, Matthew S.; Hichri, Habib; Penny, Christopher J.; Watts, David K., Method for integrating liner formation in back end of line processing.
  33. Loy, Douglas E.; Howard, Emmett; Haq, Jesmin; Munizza, Nicholas, Method for manufacturing electronic devices and electronic devices thereof.
  34. Jung, Jong Goo; Ahn, Ki Cheol; Kwon, Pan Ki, Method for manufacturing metal line contact plug of semiconductor device.
  35. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Method of electroless introduction of interconnect structures.
  36. Marrs, Michael, Method of etching organosiloxane dielectric material and semiconductor device thereof.
  37. MacDonald,Michael J., Method of forming a polishing inhibiting layer using a slurry having an additive.
  38. Michaelson,Lynne M.; Acosta,Edward; Chatterjee,Ritwik; Filipiak,Stanley M.; Garcia,Sam S.; Mathew,Varughese, Method of forming a semiconductor device having a diffusion barrier stack and structure thereof.
  39. Tonegawa,Takashi; Tsuchiya,Yasuaki; Inoue,Tomoko, Method of forming metal wiring line including using a first insulating film as a stopper film.
  40. Loy, Douglas E; Morton, David; Howard, Emmett, Method of manufacturing electronic devices on both sides of a carrier substrate and electronic devices thereof.
  41. Howard, Emmett; Munizza, Nicholas; Yee, Paul, Method of providing a flexible semiconductor device and flexible semiconductor device thereof.
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  43. Marrs, Michael A.; Howard, Emmett M.; Loy, Douglas E.; Munizza, Nicholas, Method of providing a flexible semiconductor device and flexible semiconductor device thereof.
  44. O'Rourke, Shawn; Moyer, Curtis; Ageno, Scott; Bottesch, Dirk; O'Brien, Barry; Marrs, Michael, Method of providing a flexible semiconductor device at high temperatures and flexible semiconductor device thereof.
  45. Lin,Keng Chu; Bao,Tien I; Jang,Syun Ming, Multi-level semiconductor device with capping layer for improved adhesion.
  46. Merricks, David; Goosey, Martin T.; Bains, Narinder, Plating catalysts.
  47. Choi,Hok Kin; Thirumala,Vani; Dubin,Valery; Cheng,Chin chang; Zhong,Ting, Preparation of electroless deposition solutions.
  48. Shih, Chien-Hsueh; Tsai, Minghsing; Yu, Chen-Hua; Yeh, Ming-Shih, Process for improving copper line cap formation.
  49. Shih, Chien-Hsueh; Tsai, Minghsing; Yu, Chen-Hua; Yeh, Ming-Shih, Process for improving copper line cap formation.
  50. Edelstein, Daniel C.; Colburn, Matthew E.; Cooney, III, Edward C.; Dalton, Timothy J.; Fitzsimmons, John A.; Gambino, Jeffrey P.; Huang, Elbert E.; Lane, Michael W.; McGahay, Vincent J.; Nicholson, Lee M.; Nitta, Satyanarayana V.; Purushothaman, Sampath; Sankaran, Sujatha; Shaw, Thomas M.; Simon, Andrew H.; Stamper, Anthony K., Reducing effective dielectric constant in semiconductor devices.
  51. Bonilla, Griselda; Chen, Shyng Tsong; Colburn, Matthew E.; DellaGuardia, Ronald; Yang, Chih Chao, Selective thin metal cap process.
  52. Ishikawa, Hiraku, Semiconductor device and manufacturing method thereof.
  53. Tsumura,Kazumichi; Usui,Takamasa, Semiconductor device and method for manufacturing the same.
  54. Saito,Tatsuyuki; Ohashi,Naohumi; Imai,Toshinori; Noguchi,Junji; Tamaru,Tsuyoshi, Semiconductor integrated circuit device.
  55. Saito, Tatsuyuki; Ohashi, Naohumi; Imai, Toshinori; Noguchi, Junji; Tamaru, Tsuyoshi, Semiconductor integrated circuit device and a method of manufacturing the same.
  56. Saito, Tatsuyuki; Ohashi, Naohumi; Imai, Toshinori; Noguchi, Junji; Tamaru, Tsuyoshi, Semiconductor integrated circuit device and a method of manufacturing the same.
  57. Yang, Chih-Chao; Murray, Conal E., Surface repair structure and process for interconnect applications.
  58. Wu, Yung-Hsu; Fu, Shih-Kang; Yao, Hsin-Chieh; Lee, Hsiang-Huan; Lee, Chung-Ju; Chen, Hai-Ching; Shue, Shau-Lin, System and method for chemical-mechanical planarization of a metal layer.
  59. Dubin,Valery M.; Cheng,Chin Chang; Hussein,Makarem; Nguyen,Phi L.; Brain,Ruth A., Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures.
  60. Melzner, Hanno, Vias and methods of formation thereof.
  61. Melzner, Hanno, Vias and methods of formation thereof.
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