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Method of manufacturing SOI wafer with buried layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/762
출원번호 US-0035057 (1998-03-05)
발명자 / 주소
  • Chungpin Liao TW
출원인 / 주소
  • Industrial Technology Research Institute TW
대리인 / 주소
    George O. Saile
인용정보 피인용 횟수 : 54  인용 특허 : 9

초록 ▼

A method of forming a silicon-on-insulator device having a buried layer is described. Ions are implanted into a first semiconductor substrate where it is not covered by a photoresist mask to form implanted regions. Alternatively, a silicide layer over the first semiconductor substrate is patterned t

대표청구항 ▼

1. A method of forming an integrated circuit comprising:providing a photoresist mask overlying a first semiconductor substrate; implanting ions into said first semiconductor substrate where it is not covered by said photoresist mask to form implanted regions; forming a first oxide layer overlying sa

이 특허에 인용된 특허 (9)

  1. Doyle Brian ; Yu Quat T. ; Yau Leopoldo D., Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system.
    상세보기
  2. Burke Barry E. ; Kosicki Bernard B., Interconnection technique for hybrid integrated devices.
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  3. Takahashi Kunihiro (Tokyo JPX) Kojima Yoshikazu (Tokyo JPX) Takasu Hiroaki (Tokyo JPX) Matsuyama Nobuyoshi (Tokyo JPX) Niwa Hitoshi (Tokyo JPX) Yoshino Tomoyuki (Tokyo JPX) Yamazaki Tsuneo (Tokyo JPX, Method of making light valve device using semiconductive composite substrate.
    상세보기
  4. Ramm Peter,DEX, Method of vertically integrating microelectronic systems.
    상세보기
  5. Hashimoto Naotaka,JPX ; Hoshino Yutaka,JPX ; Ikeda Shuji,JPX, Process for manufacturing semiconductor integrated circuit device.
    상세보기
  6. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
    상세보기
  7. Bendik Joseph J. (Carlsbad CA) Malloy Gerard T. (Oceanside CA) Finnila Ronald M. (Carlsbad CA), Process of manufacturing a microelectric device using a removable support substrate and etch-stop.
    상세보기
  8. Scovell Peter D. (Chelmsford GB2) Rosser Paul J. (Harlow GB2) Tomkins Gary J. (Braintree GB2), Process of self aligned nitridation of TiSi2 to form TiN/TiSi2 contact.
    상세보기
  9. Gaul Stephen Joseph ; Delgado Jose Avelino, Surface mount die by handle replacement.
    상세보기

이 특허를 인용한 특허 (54)

  1. Willard, Simon Edward; Ranta, Tero Tapio, AC coupling modules for bias ladders.
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  2. Dribinsky, Alexander; Kim, Tae Youn; Kelly, Dylan J.; Brindle, Christopher N., Circuit and method for controlling charge injection in radio frequency switches.
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  3. Shapiro, Eric S.; Allison, Matt, Circuit and method for improving ESD tolerance and switching speed.
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  4. Zahurak, John K.; Tang, Sanh D.; Heineck, Lars P.; Roberts, Martin C.; Mueller, Wolfgang; Liu, Haitao, Circuit structures, memory circuitry, and methods.
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  5. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
    상세보기
  6. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
    상세보기
  7. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
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  8. Tan, Shyue Seng; Teo, Lee Wee; Chong, Yung Fu; Quek, Elgin; Chu, Sanford, Diffusion barrier and method of formation thereof.
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  9. Bawell, Shawn; Broughton, Robert; Bacon, Peter; Greene, Robert W.; Ranta, Tero Tapio, Digitally tuned capacitors with tapered and reconfigurable quality factors.
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  10. Chen, Huajie; Chidambarrao, Dureseti; Schepis, Dominic J.; Utomo, Henry K., Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer.
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  11. Chen,Huajie; Chidambarrao,Dureseti; Schepis,Dominic J.; Utomo,Henry K., Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer.
    상세보기
  12. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
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  13. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
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  14. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
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  15. Tang, Sanh D.; Zahurak, John K.; Juengling, Werner, Floating body cell structures, devices including same, and methods for forming same.
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  16. Nobbe, Dan William; Olson, Chris; Kovac, David, Hot carrier injection compensation.
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  17. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
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  18. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
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  19. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
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  20. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
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  21. Tang, Sanh D., Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.
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  22. Tang, Sanh D., Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.
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  23. Ranta, Tero Tapio, Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device.
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  24. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
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  25. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
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  26. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
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  27. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
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  28. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
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  29. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
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  30. Bernard Aspar FR; Michel Bruel FR; Claude Jaussaud FR; Chrystelle Lagahe FR, Method for producing a thin membrane and resulting structure with membrane.
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  31. Liu, Xuefeng; Rassel, Robert M.; Voldman, Steven H., Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate.
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  32. Reedy, Ronald Eugene; Nobbe, Dan William; Ranta, Tero Tapio; Liss, Cheryl V.; Kovac, David, Methods and apparatuses for use in tuning reactance in a circuit device.
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  33. Ranta, Tero Tapio, Positive logic digitally tunable capacitor.
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  34. Facchini, Marc; Bacon, Peter, Power splitter with programmable output phase shift.
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  35. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
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  36. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
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  37. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
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  38. Tang, Sanh D.; Zahurak, John K., Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same.
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  39. Tang, Sanh D.; Zhang, Ming, Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices.
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  40. Tang, Sanh D.; Zhang, Ming, Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices.
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  41. Olson, Chris, Semiconductor devices with switchable ground-body connection.
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  42. Carroll, Michael; Kerr, Daniel Charles; Iversen, Christian Rye; Mason, Philip; Costa, Julio; Spears, Edward T., Semiconductor radio frequency switch with body contact.
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  43. Tang, Sanh D.; Zhang, Ming; Bayless, Andrew M.; Zahurak, John K., Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures.
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  44. Liu, Xuefeng; Rassel, Robert M.; Voldman, Steven H., Si and SiGeC on a buried oxide layer on a substrate.
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  45. Liu, Xuefeng; Rassel, Robert M.; Voldman, Steven H., Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology.
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  46. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
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  47. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
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  48. Tang, Sanh D., Thyristor based memory cells, devices and systems including the same and methods for forming the same.
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  49. Tang, Sanh D., Thyristor-based memory cells, devices and systems including the same and methods for forming the same.
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  50. Tang, Sanh D., Thyristor-based memory cells, devices and systems including the same and methods for forming the same.
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  51. Nemati, Farid; Robins, Scott T.; Gupta, Rajesh N., Thyristors.
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  52. Nemati, Farid; Robins, Scott T.; Gupta, Rajesh N., Thyristors, methods of programming thyristors, and methods of forming thyristors.
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  53. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
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  54. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
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