초록 ▼

A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input

A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). Each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD.

대표청구항 ▼

1. In a programmable logic device, a lookup table (LUT) operable as a shift register comprising:a plurality of memory cells each having inverting and noninverting nodes; for each of the memory cells, a dynamic output latch comprising an inverter and a transistor connected between an input terminal o

1. In a programmable logic device, a lookup table (LUT) operable as a shift register comprising:a plurality of memory cells each having inverting and noninverting nodes; for each of the memory cells, a dynamic output latch comprising an inverter and a transistor connected between an input terminal of the inverter and one of the inverting and noninverting nodes; a shift-in line connected by a shift-in transistor between an output terminal of the inverter of a first memory cell and one of the inverting and noninverting nodes of a second memory cell, and further controlling voltage on another of the inverting and noninverting nodes of the second memory cell.