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Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-022/44
출원번호 US-0076565 (1998-05-12)
발명자 / 주소
  • E. Henry Stevens
출원인 / 주소
  • Semitool, Inc.
대리인 / 주소
    Polit & Associates, LLC
인용정보 피인용 횟수 : 38  인용 특허 : 2

초록

A process for providing one or more protected copper elements on a surface of a workpiece is set forth. In accordance with the process, a barrier layer is applied to the workpiece. If the barrier layer is not suitable as a seed layer for subsequent electroplating processes, a separate seed layer is

대표청구항

1. A process for providing one or more protected copper elements on a surface of a workpiece, the process comprising the steps of:applying a barrier layer to the workpiece; applying a seed layer on the barrier layer; electroplating one or more copper elements on selected portions of the seed layer;

이 특허에 인용된 특허 (2)

  1. Uno Hiroaki,JPX ; Kawade Masato,JPX, Multilayer printed circuit board and method of producing the same.
  2. Nguyen Tue ; Charneski Lawrence J. ; Allen Lynn R., Oxidized diffusion barrier surface for the adherence of copper and method for same.

이 특허를 인용한 특허 (38)

  1. Ogura, Ken, Conductor posts, construction for and method of fabricating semiconductor integrated circuit chips using the conductor post, and method of probing semiconductor integrated circuit chips.
  2. Bresler,Joel; Raffel,Jack, Method and system for locating position in printed texts and delivering multimedia information.
  3. Cheung, Robin; Chen, Liang-Yuh, Method of forming copper interconnects.
  4. Zhang, Fengyan; Maa, Jer-shen; Hsu, Sheng Teng, Method of forming iridium conductive electrode/barrier structure.
  5. Jaw, Kou-Liang; Chen, Jen-Te, Method of power IC inspection.
  6. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  7. Uzoh, Cyprian E.; Locke, Peter S., Seedlayer for plating metal in deep submicron structures.
  8. Imamura, Tomomi; Matsuda, Tetsuo; Nishijo, Yoshinosuke, Semiconductor device and method for manufacturing of same.
  9. Imamura, Tomomi; Matsuda, Tetsuo; Nishijo, Yoshinosuke, Semiconductor device and method for manufacturing of same.
  10. Imamura, Tomomi; Matsuda, Tetsuo; Nishijo, Yoshinosuke, Semiconductor device and method for manufacturing of same.
  11. Cheung,Robin W.; Sinha,Ashok K., Semiconductor device interconnect fabricating techniques.
  12. Collins,Dale W., Semiconductor having a substantially uniform layer of electroplated metal.
  13. Patton, Evan E.; Cacouris, Theodore; Broadbent, Eliot; Mayer, Steven T., Sequential station tool for wet processing of semiconductor wafers.
  14. Patton, Evan E.; Cacouris, Theodore; Broadbent, Eliot; Mayer, Steven T., Sequential station tool for wet processing of semiconductor wafers.
  15. Patton, Evan E.; Cacouris, Theodore; Broadbent, Eliot; Mayer, Steven T., Sequential station tool for wet processing of semiconductor wafers.
  16. D'Ambra,Allen L.; Shanmugasundram,Arulkumar; Yang,Michael X.; Rabinovich,Yevgeniy (Eugene); Lubomirsky,Dmitry, Slim cell platform plumbing.
  17. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  18. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  19. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  20. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  26. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  27. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  30. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  31. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  32. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  33. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  34. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  35. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  36. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  37. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  38. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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