초록 ▼

A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an inter

A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.

대표청구항 ▼

1. A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the steps of:providing a semiconductor wafer structure having at least an upper and a lower dielectric layer; said semiconductor wafer structure having a bonding pad area and a interconnect

1. A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the steps of:providing a semiconductor wafer structure having at least an upper and a lower dielectric layer; said semiconductor wafer structure having a bonding pad area and a interconnect area; forming, at least one active interconnect having a first width, in said interconnect area, through said dielectric layers, and a plurality of adjacent dummy plugs each having a second width, in said bonding pad area, through a portion of said dielectric layers; patterning and etching said semiconductor wafer structure to form trenches through said upper dielectric layer; said trenches surrounding each of said at least one active interconnect and said dummy plugs whereby said upper dielectric level between said adjacent dummy plugs is removed; depositing a metallization layer over said lower dielectric layer, filling said trenches at least to the upper surface of the remaining upper dielectric layer; and planarizing said metallization layer to remove the excess of said metallization layer forming a continuous bonding pad within said bonding pad area and including said plurality of adjacent dummy plugs; and forming at least one damascene structure including said at least one respective active interconnect.