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Apparatus and method for serial data communication between plurality of chips in a chip set

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04L-023/00
출원번호 US-0241729 (1999-02-02)
발명자 / 주소
  • David Lee TW
  • Cheng-Wang Huang TW
출원인 / 주소
  • United Microelectronics Corp. TW
인용정보 피인용 횟수 : 54  인용 특허 : 2

초록

An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request fro

대표청구항

1. An apparatus for serial data communication between a first IC chip and a second IC chip, the apparatus receiving a synchronization clock signal from an external circuit, the synchronization clock signal having a plurality of cycle periods, the apparatus comprising:a transfer request signal genera

이 특허에 인용된 특허 (2)

  1. Taniai Takayoshi (Kawasaki JPX) Tanaka Yasuhiro (Koshigaya JPX) Saitoh Tadashi (Kawasaki JPX), Direct memory access controller for handling cyclic execution of data transfer in accordance with stored transfer contro.
  2. Muramatsu Tsuyoshi (Tenri JPX) Onozaki Manabu (Nara JPX), Self-timed clocking transfer control circuit.

이 특허를 인용한 특허 (54)

  1. Whinnett, Nicholas William; Somerville, Fiona Clare Angharad, Accessing a base station.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  8. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  9. Park, Jae-Young, Apparatus and method for exchanging status information between boards.
  10. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Nolan, John Matthew; Dealtry, Roger Paul, Array synchronization with counters.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann,W. James; Hogenauer,Eugene B., Data distributor in a computation unit forwarding network data to select components in respective communication method type.
  20. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  22. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  25. Whinnett, Nick; Somerville, Fiona, Femtocell access control.
  26. Whinnett, Nick; Somerville, Fiona; Smart, Christopher, Femtocell base station.
  27. Smart, Christopher Brian, Filter.
  28. Kondo, Nobukazu; Noguchi, Koki; Kawasaki, Ikuya, Information processing apparatus.
  29. Kondo, Nobukazu; Kawasaki, Ikuya; Noguchi, Koki, Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system.
  30. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas, Input/output controller node in an adaptable computing environment.
  31. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  32. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  33. Whinnett, Nicholas William, Method and device in a communication network.
  34. Whinnett, Nicholas William, Method and device in a communication network.
  35. Whinnett, Nicholas William, Method and device in a communication network.
  36. Whinnett, Nicholas William, Method and device in a communication network.
  37. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  38. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  41. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  42. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  44. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  45. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  46. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  47. Whinnett, Nick, Methods and devices for reducing interference in an uplink.
  48. Smart, Christopher Brian, Power control.
  49. Scheuermann,W. James, Processing architecture for a reconfigurable arithmetic node.
  50. Claydon, Anthony Peter John; Claydon, Anne Patricia, Processor architecture with switch matrices for transferring data along buses.
  51. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  52. Master,Paul L.; Watson,John, Storage and delivery of device features.
  53. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  54. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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