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Method of forming a transistor gate

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/336
  • H01L-021/31
  • H01L-021/469
출원번호 US-0852449 (2001-05-09)
발명자 / 주소
  • Randhir P. S. Thakur
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Wells St. John P.S.
인용정보 피인용 횟수 : 5  인용 특허 : 27

초록

A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vap

대표청구항

1. A method of forming a transistor gate construction comprising:providing a semiconductive region of a substrate to be gated; providing a conductive transistor gate proximate the region to be gated; providing a gate dielectric layer intermediate the region to be gated and the transistor gate, the g

이 특허에 인용된 특허 (27)

  1. Davis Cecil J. (Greenville TX) Spencer John E. (Plano TX) Johnson Randall E. (Carrollton TX) Jucha Rhett B. (Celeste TX) Brown Frederick W. (Tarrant TX) Kohan Stanford P. (Garland TX), Automated single slice cassette load lock plasma reactor.
  2. Hirayama Makoto (Hyogo JPX), Electronic component having improved low resistance contact and manufacturing method therefor.
  3. Thompson Richard B. ; Patchan Marcia W. ; Ge Zhenfang, Enzyme-based fluorescence biosensor for chemical analysis.
  4. Xiang Qi ; Lin Ming-Ren, Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant.
  5. Schuegraf Klaus F. (Boise ID) Thakur Randhir P. S. (Boise ID) Fazan Pierre C. (Boise ID), High pressure reoxidation anneal of silicon nitride for reduced thermal budget silicon processing.
  6. Sasuga Masumi (Mobara JPX) Ohwada Junichi (Mobara JPX) Kobayashi Akira (Mobara JPX) Fujita Masaru (Mobara JPX) Nakamoto Hiroshi (Mobara JPX) Ono Ryu (Chiba JPX) Isono Tsutomu (Ohtaki JPX), Liquid crystal display device with shield casing connected to frame holding the display above lower casing holding light.
  7. Oguro Shizuo (Tokyo JPX), Method for fabricating capacitor having polycrystalline silicon film.
  8. Sandhu Gurtej S. (Boise ID) Thakur Randhir P. S. (Boise ID), Method for fabricating stacked layer Si3N4 for low leakage high capacitance films using rapi.
  9. Schuegraf Klaus Florian, Method for forming a capacitor.
  10. Hwang Ki-hyun,KRX ; Park Jae-young,KRX ; Byun Jae-ho,KRX, Method for forming a tantalum oxide capacitor using two-step rapid thermal nitridation.
  11. Yokozawa Ayumi (Tokyo JPX), Method for forming silicon nitride film having low leakage current and high break down voltage.
  12. Mercaldi Garry A. ; Nuttall Michael L. ; Thankur Randhir P. S., Method for optimization of thin film deposition.
  13. Huanga Julie (Hsin-Chu TWX) Liang Mong-Song (Hsin-Chu TWX), Method of forming an ultra thin dielectric film for a capacitor.
  14. DeBoer Scott Jeffrey ; Gealy F. Daniel ; Thakur Randhir P. S., Method of forming capacitors containing tantalum.
  15. Inoue Nobuhiko,JPX, Method of manufacturing semiconductor device.
  16. Zenke Masanobu,JPX, Method of manufacturing semiconductor device.
  17. Watanabe Hirohito (Tokyo JPX) Ohnishi Sadayuki (Tokyo JPX), Method of producing semiconductor device with insulating film having at least silicon nitride film.
  18. Hwang Chorng-Lii (Wappingers Falls NY) Teng Clarence W. (Plano TX), Microplanarization of rough electrodes by thin amorphous layers.
  19. Okamura Ryuji (Ika JPX) Otoshi Hirokazu (Nagahama JPX) Takei Tetsuya (Nagahama JPX), Process and apparatus for the formation of a functional deposited film on a cylindrical substrate by means of microwave.
  20. Meyer Glenn Allyn ; Ciarlo Dino R. ; Myers Booth Richard ; Chen Hao-Lin ; Wakalopulos George, Rigid thin windows for vacuum applications.
  21. Goth George R. (Poughkeepsie NY) Magdo Ingrid E. (Hopewell Junction NY) Malaviya Shashi D. (Fishkill NY), Self-aligned metal process for integrated circuit metallization.
  22. Ohi Makoto (Hyogo-ken JPX) Arima Hideaki (Hyogo-ken JPX) Ajika Natsuo (Hyogo-ken JPX), Semiconductor device having capacitor and manufacturing method therefor.
  23. Ohji Yuzuru (Nishitama JPX) Kasahara Osamu (Nishitama JPX) Tadaki Yoshitaka (Ome JPX) Kaneko Hiroko (Higashimurayama JPX) Mine Toshiyuki (Nishitama JPX) Yagi Kunihiro (Nishitama JPX), Semiconductor device with multilayer silicon oxide silicon nitride dielectric.
  24. Schuegraf Klaus, Semiconductor processing method of forming a capacitor and capacitor constructions.
  25. Blazevich John Z., Serving tray with shrimp.
  26. Inaba Yutaka (Hyogo JPX) Kobayashi Kiyoteru (Hyogo JPX), Silicon nitride film formation method.
  27. Pedder David J. (Long Compton GB3), Trimmable capacitor.

이 특허를 인용한 특허 (5)

  1. Orihashi, Yugo; Moriya, Atsushi, Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium.
  2. Thakur, Randhir P. S., Methods to form electronic devices.
  3. Thakur, Randhir P. S., Methods to form electronic devices and methods to form a material over a semiconductive substrate.
  4. Thakur,Randhir P.S., Methods to form electronic devices and methods to form a material over a semiconductive substrate.
  5. Narwankar, Pravin K.; Miner, Gary E.; Lepert, Arnaud, Tailoring nitrogen profile in silicon oxynitride using rapid thermal annealing with ammonia under ultra-low pressure.

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