초록 ▼

A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate polysilicon layer. Impurity i

A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate polysilicon layer. Impurity ions are implanted and diffused using the gate spacer and the gate polysilicon layer as a mask layer to form a source/drain region in the substrate. An etching blocking layer is formed to cover the source/drain region, the gate spacer, and the gate polysilicon layer, and then, a dielectric layer to cover the etching blocking layer is formed. The dielectric layer is planarized, and the etching blocking layer on the gate polysilicon layer is exposed. The exposed etching blocking layer and a part of the gate spacer are etched, and a top surface and a top side of the gate polysilicon layer are exposed. A silicide layer is formed over the exposed part of the gate polysilicon layer.

대표청구항 ▼

1. A method for fabricating a MOS transistor comprising the steps of:sequentially forming a gate insulating layer and a gate polysilicon layer on a substrate; forming a gate spacer on a side wall of the gate insulating layer and the gate polysilicon layer; implanting and diffusing impurity ions into

1. A method for fabricating a MOS transistor comprising the steps of:sequentially forming a gate insulating layer and a gate polysilicon layer on a substrate; forming a gate spacer on a side wall of the gate insulating layer and the gate polysilicon layer; implanting and diffusing impurity ions into the substrate, using the gate spacer and the gate polysilicon layer as a mask layer, thereby forming a source/drain region on the substrate; forming an etching blocking layer to cover the source/drain region, the gate spacer, and the gate polysilicon layer; forming a dielectric layer to cover the etching blocking layer; planarizing the dielectric layer and exposing the etching blocking layer on the gate polysilicon layer; etching the exposed etching blocking layer and a part of the gate spacer, and exposing a top surface and a top side of the gate polysilicon layer; and selectively forming a silicide layer on the exposed gate polysilicon layer.