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Top layers of metal for high performance IC's 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/28
출원번호 US-0251183 (1999-02-17)
발명자 / 주소
  • Mou-Shiung Lin TW
출원인 / 주소
  • M. S. Lin TW
대리인 / 주소
    George O. Saile
인용정보 피인용 횟수 : 189  인용 특허 : 7

초록

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide polymer as an inter-metal dielectric thus enabling

대표청구항

1. A method for forming a top metallization system for high performance integrated circuits, comprising:forming an integrated circuit containing a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and

이 특허에 인용된 특허 (7)

  1. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method.
  2. Cronin John Edward, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.
  3. Yamada Yoshiaki,JPX, Method for fabricating a semiconductor device having a refractory metal pillar for electrical connection.
  4. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines.
  5. Yamada Yoshiaki,JPX, Method of manufacturing a semiconductor device using a silicon fluoride oxide film.
  6. Nguyen Chanh N. ; Nguyen Nguyen Xuan ; Le Minh V., Modulation-doped field-effect transistors and fabrication processes.
  7. Yu Sun-il,KRX ; Kang Woo-tag,KRX, Semiconductor-on-insulator devices having insulating layers therein with self-aligned openings.

이 특허를 인용한 특허 (189)

  1. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
  2. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
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  7. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
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  11. Lin, Mou-Shiung, Chip package and method for fabricating the same.
  12. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  14. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip package with die and substrate.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  16. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
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  19. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  20. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.
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  24. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip.
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  36. Lin, Mou Shiung, High performance system-on-chip passive device using post passivation process.
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  40. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
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  70. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
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  184. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
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  186. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

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