초록 ▼

The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory a

The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.

대표청구항 ▼

1. A nonvolatile memory cell wherein first and second impurity regions of a first conductivity type are formed in a main surface of a substrate and separated therebetween by a channel forming semiconductor region of a second conductivity type in said main surface of said substrate the first conducti

1. A nonvolatile memory cell wherein first and second impurity regions of a first conductivity type are formed in a main surface of a substrate and separated therebetween by a channel forming semiconductor region of a second conductivity type in said main surface of said substrate the first conductivity type is opposite the second conductivity type, a gate electrode is formed on a gate insulator on said channel forming semiconductor region, and carriers are being injected and stored in a carrier trapping means of said gate insulator further comprising:an acceleration-electrical potential supplying means to selectively supply an acceleration-electrical potential to one out of the first and second impurity regions at one side; said channel forming semiconductor region includes a carrier-supplying portion and a carrier-acceleration-injection portion disposed along a carrier transport direction; said carrier-supplying portion supplies to said carrier-acceleration-injection portion carriers supplied by another one out of said first and second impurity regions at another side; said carrier-acceleration-injection portion makes local injection of carriers supplied from said carrier-supplying portion into said gate insulator in the vicinity of the adjacent said one out of said first and second impurity regions at one side to which said accelerated electrical potential is supplied; said carrier-acceleration-injection portion comprises a first carrier-acceleration-injection portion formed adjacent to said first impurity region and a second carrier-acceleration-injection portion adjacent to said second impurity region said carrier-supplying portion is disposed between said first carrier-acceleration-injection portion and said second carrier-acceleration-injection portion; said gate insulator is comprised of a first gate insulator disposed on said carrier-supplying portion and two second gate insulators disposed on said first carrier-acceleration-injection portion and said second carrier-acceleration-injection portion, respectively; said carrier trapping means is in said second gate insulators; said acceleration-electrical supplying means supplies an acceleration-electrical potential to said second impurity region when injecting carriers from said second carrier-acceleration-injection portion into a second one of said second gate insulators and to said first impurity region when injecting carriers from said first carrier-acceleration-injection portion into a first one of said second gate insulators; and said gate electrode is comprised of a first gate electrode and two second gate electrodes wherein said first gate electrode, a first one of said second gate electrodes and a second one of said second gate electrodes are insulated from each other, wherein said first gate electrode is disposed above said carrier-supplying portion through said first gate insulator and said first one of said second gate electrodes is disposed above said first carrier-acceleration-injection portion through said first one of said second gate insulators, and wherein said second one of said second gate electrodes is disposed above said second carrier-acceleration-injection portion through said second one of said second gate insulators.