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Electrically programmable antifuses and methods for forming the same

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
출원번호 US-0466495 (1999-12-17)
발명자 / 주소
  • Claude L. Bertin
  • Erik L. Hedberg
  • Russell J. Houghton
  • Max G. Levy
  • Rick L. Mohler
  • William R. Tonti
  • Wayne M. Trickle
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    DeLio & Peterson, LLC
인용정보 피인용 횟수 : 31  인용 특허 : 36

초록

A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the

대표청구항

1. A one time, voltage programmable logic element in a semiconductor substrate of first conductivity type comprising:a first layer beneath a surface of the substrate, the first layer having a second conductivity type; a trench formed through the surface and passing through the first layer, the trenc

이 특허에 인용된 특허 (36)

  1. Cervin-Lawry Andrew V. C.,CAX ; Kendall James D.,CAX ; Appelman Petrus T.,CAX ; Roubakha Efim,CAX, Antifuse based on silicided polysilicon bipolar transistor.
  2. Sher Joseph C. (Boise ID) Keeth Brent (Boise ID), Antifuse programming method and apparatus.
  3. Iranmanesh Ali A. (Sunnyvale CA), Antifuse with silicon spacers.
  4. McElroy David J. (Houston TX), Avalanche fuse element as programmable device.
  5. Li Xiao-Yu ; Barsan Radu ; Mehta Sunil D., Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide.
  6. Chen Wenn-Jei (Sunnyvale CA) Tseng Huan-Chung (Santa Clara CA) Yen Yeouchung (San Jose CA) Liu Linda (San Jose CA), ESD protection device for antifuses with top polysilicon electrode.
  7. Chen Wenn-Jei (Sunnyvale CA) Tseng Huang-Chung (Santa Clara CA), Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of.
  8. Bracchitta John A. ; Pricer Wilbur D., Electrically alterable antifuse using FET.
  9. Gambino Jeffrey P. (Gaylordsville CT) Schepis Dominic J. (Wappingers Falls NY) Seshan Krishna (Beacon NY), Electrically programmable antifuse using metal penetration of a junction.
  10. Cohen Simon S. (Burlington MA), Electrically programmable link structures and methods of making same.
  11. Lee Roger R. (Boise ID), Electrically programmable low resistive antifuse element.
  12. Mohsen, Amr M.; Crook, Dwight L., Fusible link employing capacitor structure.
  13. Tung Ming-Tsung,TWX, High-voltage semiconductor device with trench structure.
  14. Lee Roger R. (Boise ID), Local field enhancement for better programmability of antifuse PROM.
  15. Duesman Kevin G., Memory-cell array and a method for repairing the same.
  16. Blanchard Richard A. (Los Altos CA), Method for making planar vertical channel DMOS structures.
  17. Look Kevin T. ; Karpovich Yakov ; Hart Michael J., Method for over-etching to improve voltage distribution.
  18. Yindeepol Wipawan ; McGregor Joel ; Bashir Rashid ; Brown Kevin ; DeSantis Joseph Anthony, Method of forming and planarizing deep isolation trenches in a silicon-on-insulator (SOI) structure.
  19. Lowrey Tyler A. (Boise ID) Duesman Kevin G. (Boise ID) Cloud Eugene H. (Boise ID), Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM.
  20. Zheng Jiazhen (Singapore SGX) Chan Lap (San Francisco CA), Method of making a dual damascene antifuse structure.
  21. Chor Calvin Leung Yat (Singapore SGX), Method of making an antifuse cell with tungsten silicide electrode.
  22. Assaderaghi Fariborz ; Hsu Louis L. ; Mandelman Jack A. ; Tonti William R., Method of making large value capacitor for SOI.
  23. Beyer Klaus D. (Poughkeepsie NY) Silvestri Victor J. (Hopewell Junction NY), Method of trench filling.
  24. Hart Michael J. ; Look Kevin T. ; Karpovich Yakov, Multilayer amorphous silicon antifuse.
  25. Lowrey Tyler A. (Boise ID) Lee Ruojia (Boise ID), One-time, voltage-programmable, logic element.
  26. Brown Alan E. (Georgetown TX), Over temperature memory circuit.
  27. Choi Kyu H. (Santa Clara CA), Programmable interconnect device and method of manufacturing same.
  28. Shimanek Schuyler E. (Albuquerque NM) Anderson Alma (Rio Rancho NM), Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, val.
  29. Lee Steven S. (Colorado Springs CO) Miller Gayle W. (Colorado Springs CO), Semiconductor fuse and method.
  30. He Yue Song ; Liu Yowjuang William, Semiconductor isolation process to minimize weak oxide problems.
  31. Abe Hirofumi (Okazaki JPX) Shibata Tadashi (Toyokawa JPX), Semiconductor programmable read only memory device.
  32. Peidous Igor V.,SGX, Shallow trench isolation of MOSFETS with reduced corner parasitic currents.
  33. Blankenship Timothy L. (Palm Bay FL) Nolan ; III Joseph G. (San Jose CA), Test circuitry for testing fuse link programmable memory devices.
  34. Lee Roger R. (Boise ID), Transistor antifuse for a programmable ROM.
  35. Omid-Zohoor Farrokh, Trench isolation with suppressed parasitic edge transistors.
  36. Horak David Vaclav ; Furukawa Toshiharu ; Holmes Steven John ; Hakey Mark Charles ; Ma William Hsioh-Lien ; Mandelman Jack Allan, Trench storage dram cell including a step transfer device.

이 특허를 인용한 특허 (31)

  1. Wilcox, William J., Antifuse circuit with well bias transistor.
  2. Wilcox, William J., Antifuse circuit with well bias transistor.
  3. Min, Won Gi; Perkins, Geoffrey W.; Zukowski, Kyle D.; Zuo, Jiang-Kai, Antifuses with curved breakdown regions.
  4. Toomey, James J., Bridge for semiconductor internal node.
  5. Toomey,James J., Bridge for semiconductor internal node.
  6. Cestero, Alberto; Park, Byeongju; Safran, John M., Electrical antifuse.
  7. Kim, Deok-kee; Kim, Hoki; Kothandaraman, Chandrasekharan; Park, Byeongju; Safran, John M., Electrical antifuse with integrated sensor.
  8. Iyer, Subramanian S.; Kim, Deok-Kee; Kothandaraman, Chandrasekharan; Park, Byeongju, Electrical fuse structure for higher post-programming resistance.
  9. Kothandaraman,Chandrasekharan; Maciejewski,Edward P., Electrically programmable fuse for silicon-on-insulator (SOI) technology.
  10. Radens, Carl J.; Tonti, William R., MOS antifuse with low post-program resistance.
  11. Radens,Carl J.; Tonti,William R., MOS antifuse with low post-program resistance.
  12. Ito, Akira; Smith, Douglas D.; Buer, Myron J., Method for making MOSFET anti-fuse structure.
  13. Chen,Xiaomeng; Jeng,Shwu Jen; Kim,Byeong Y.; Nayfeh,Hasan M., Method of making a semiconductor structure.
  14. Cestero, Alberto; Park, Byeongju; Safran, John M., Method of manufacturing an electrical antifuse.
  15. Cestero, Alberto; Park, Byeongju; Safran, John M., Method of programming electrical antifuse.
  16. Kim, Deok-kee; Wong, Keith Kwong Hon; Yang, Chih-Chao; Yang, Haining S., Methods and systems involving electrically programmable fuses.
  17. Min, Won Gi; Perkins, Geoffrey W.; Zukowski, Kyle D.; Zuo, Jiang-Kai, Methods for forming antifuses with curved breakdown regions.
  18. Chinthakindi, Anil K.; Kim, Deok-Kee; Li, Xi, Post STI trench capacitor.
  19. Chinthakindi, Anil K.; Kim, Deok-kee; Li, Xi, Post STI trench capacitor.
  20. Kothandaraman,Chandrasekharan; Iyer,Subramanian, Programmable electronic fuse.
  21. Kreipl, Dwayne, Recessed gate dielectric antifuse.
  22. Kreipl, Dwayne, Recessed gate dielectric antifuse.
  23. Kreipl, Dwayne, Recessed gate dielectric antifuse.
  24. Fukuzumi, Yoshiaki; Kohyama, Yusuke, Semiconductor device using fuse/anti-fuse system.
  25. Fukuzumi, Yoshiaki; Kohyama, Yusuke, Semiconductor device using fuse/anti-fuse system.
  26. Radens, Carl J.; Bergner, Wolfgang; Divakaruni, Rama; Nesbit, Larry, Semiconductor fuses and antifuses in vertical DRAMS.
  27. Porter,Stephen R., Shallow trench antifuse and methods of making and using same.
  28. Park,Byeongju; Safran,John M., System and method for increasing reliability of electrical fuse programming.
  29. Kim, Deok-kee; Park, Byeongju; Safran, John M., Transistor based antifuse with integrated heating element.
  30. Booth, Jr., Roger A.; Cheng, Kangguo; Mandelman, Jack A.; Tonti, William R., Trench anti-fuse structures for a programmable integrated circuit.
  31. Cheng, Kangguo; Li, Juntao; Wang, Geng; Zhang, Qintao, Vertical antifuse structures.
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