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A logic element for a programmable logic device (PLD) can be configured as a shift register of variable length. An array of memory cells in the logic element is divided into two or more portions. The memory cells of each portion supply values to a corresponding output multiplexing circuit, thereby e

A logic element for a programmable logic device (PLD) can be configured as a shift register of variable length. An array of memory cells in the logic element is divided into two or more portions. The memory cells of each portion supply values to a corresponding output multiplexing circuit, thereby enabling the logic element to function as a lookup table by combining the outputs of the multiplexing circuits. However, each portion is also configurable as a shift register. The portions can function as separate shift registers, or can be concatenated to function as a single shift register. In some embodiments, the portions can also be concatenated with shift registers in other logic elements. Because two or more output multiplexing circuits are available, two or more taps are provided, one from each portion of the memory array.

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1. A logic element for a Programmable Logic Device (PLD), comprising:an array of memory cells; a first multiplexing circuit; a first plurality of memory cells in the array, each memory cell having a shift in terminal and a shift out terminal, with the shift out terminal of one memory cell being coup

1. A logic element for a Programmable Logic Device (PLD), comprising:an array of memory cells; a first multiplexing circuit; a first plurality of memory cells in the array, each memory cell having a shift in terminal and a shift out terminal, with the shift out terminal of one memory cell being coupled to the shift in terminal of a next memory cell, thereby forming a first shift register having a first memory cell and a last memory cell, wherein each memory cell in the first shift register provides a data value stored in the memory cell to the first multiplexing circuit, and wherein the last memory cell in the first shift register provides a first shift register out signal; a second multiplexing circuit; a second plurality of memory cells in the array, each memory cell having a shift in terminal and a shift out terminal, with the shift out terminal of one memory cell being coupled to the shift in terminal of a next memory cell, thereby forming a second shift register having a first memory cell and a last memory cell, wherein each memory cell in the second shift register provides a data value stored in the memory cell to the second multiplexing circuit, and the last memory cell in the second shift register provides a second shift register out signal; and a third multiplexing circuit providing a signal to the shift in terminal of the first memory cell in the second shift register, the third multiplexing circuit selecting at least between the first shift register out signal and an output of the first multiplexing circuit.