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Column grid array substrate attachment with heat sink stress relief 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/03
출원번호 US-0688073 (1996-07-29)
발명자 / 주소
  • Robert Charles Dockerty
  • Ronald Maurice Fraga
  • Ciro Neal Ramirez
  • Sudipta Kumar Ray
  • Gordon Jay Robbins
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Casimer K. Salys
인용정보 피인용 횟수 : 20  인용 특허 : 32

초록

Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention in

대표청구항

1. In a system for connecting a substrate having a low coefficient of thermal expansion to a printed circuit board having a materially higher coefficient of thermal expansion using an array of solder columns and reflow bonding, a supporting structure with effective heat sink coupling to the substrat

이 특허에 인용된 특허 (32)

  1. Leicht John L. (Hawthorn Woods IL) Bratschun William R. (La Grange IL), Alloy solder connect assembly and method of connection.
  2. Ho Tony H. (Hsin-Chu TWX), Ball grid array having reduced mechanical stress.
  3. Covell ; II James H. ; Bolde Lannie R. ; Edwards David L. ; Goldmann Lewis S. ; Gruber Peter A. ; Toy Hilton T., Cast metal seal for semiconductor substrates and process thereof.
  4. Allen Leslie J. (Swindon CA GB2) Cherian Gabe (Fremont CA) Diaz Stephen H. (Los Altos CA), Chip carrier mounting device.
  5. Allen Leslie J. (Swindon CA GB2) Cherian Gabe (Fremont CA) Diaz Stephen H. (Los Altos CA), Chip mounting device.
  6. Baldwin Graham J. (Cheltenham GB2) McCann Michael O. (Wotton-Under-Edge GB2), Chip-carrier substrates.
  7. Missele Carl (Elgin IL), Compliant solder interconnection.
  8. Kohara, Masanobu; Nakao, Shin; Shibata, Hiroshi, Dimensionally stable semiconductor device.
  9. Warner David J. (Northampton GB2) Pickering Kim L. (Northampton GB2) Pedder David J. (Warwickshire GB2), Flip chip solder bond structure for devices with gold based metallization.
  10. Swamy Deepak (12330 Metric Blvd. ; #5206 Austin TX 78758) Lunsford David (23022 Pedernales Canyon Austin TX 78669), Hybrid multichip module and methods of fabricating same.
  11. Chiu George W. (Palo Alto CA), Laminated solder column.
  12. Jones Tim (Chandler AZ) Ommen Denise (Phoenix AZ) Baird John (Scottsdale AZ), Low-profile ball-grid array semiconductor package.
  13. Schelhorn Robert L. (Vincentown NJ), Method for connecting a leadless chip carrier to a substrate.
  14. Myers Bruce A. (Kokomo IN) Schnabel Petrina L. (Kokomo IN), Method for controlling solder bump height for flip chip integrated circuit devices.
  15. Lynch James Edward (Harrisburg Middletown PA) Fussleman David Francis (Middletown PA), Method of connecting terminal posts of a connector to a circuit board.
  16. Granier Francois J. (Montpellier FRX) Rieu Jean-Jacques M. (Baillargues FRX) Raout Philippe (Saint Selve FRX) Sanchez Andre (Saint Aunes FRX), Method of fabricating an electronic interconnection.
  17. Agarwala Birendra N. (Hopewell Junction NY) Ahsan Aziz M. (Hopewell Junction NY) Bross Arthur (Poughkeepsie NY) Chadurjian Mark F. (Essex Junction VT) Koopman Nicholas G. (Hopewell Junction NY) Lee L, Method of forming dual height solder interconnections.
  18. Liang Dexin (Fremont CA) Schneider Mark R. (San Jose CA), Microelectronic integrated circuit mounted on circuit board with solder column grid array interconnection, and method of.
  19. Covell ; II James Howard ; Braun Carol Jill, Mold transfer apparatus and method.
  20. Edwards David L. ; Cammarano Armando S. ; Coffin Jeffrey T. ; Courtney Mark G. ; Drofitz ; Jr. Stephen S. ; Ellsworth ; Jr. Michael J. ; Goldmann Lewis S. ; Iruvanti Sushumna ; Pompeo Frank L. ; Sabl, Multi-layer solder seal band for semiconductor substrates.
  21. Edwards David L. ; Cammarano Armando S. ; Coffin Jeffrey T. ; Courtney Mark G. ; Drofitz ; Jr. Stephen S. ; Ellsworth ; Jr. Michael J. ; Goldmann Lewis S. ; Iruvanti Sushumna ; Pompeo Frank L. ; Sabl, Multi-layer solder seal band for semiconductor substrates and process.
  22. Melton Cynthia M. (Bolingbrook IL) Raleigh Carl J. (Cary IL) Scheifers Steven (Hoffman Estates IL), Noncollapsing multisolder interconnection.
  23. Brown Vernon L. (Boulder CO), Printed wiring board construction.
  24. LoVasco Francis (Roxbury Township NJ) Oien Michael A. (Chatham Township ; both of Morris County NJ), Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate.
  25. Behun John R. (Poughkeepsie NY) Miller William R. (Poughkeepsie NY) Newman Bert H. (Carmel NY) Yankowski Edward L. (Hyde Park NY), Process of fabricating a circuit package.
  26. Beckham Keith F. (Newburgh NY) Kolman Anne E. (Wappingers Falls NY) McGuire Kathleen M. (Fishkill NY) Puttlitz Karl J. (Wappingers Falls NY) Quinones Horatio (Peekskill NY), Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and pr.
  27. Gaudenzi Gene J. (Purdys NY) Mosley Joseph M. (Boca Raton FL) Tuozzolo Vito J. (Boca Raton FL) Milliken John C. (Patterson NY), Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arra.
  28. Dixon D. Craig (Lewisville TX) Hundt Michael J. (Double Oak TX), Surface mountable integrated circuit package with integrated battery mount.
  29. Hill Peter F. (Hatfield GB2), Surface mounting leadless components on conductor pattern supporting substrates.
  30. Visel Thomas A. (Phoenix AZ) Long Jon M. (Livermore CA), System for securing and electrically connecting a semiconductor chip to a substrate.
  31. Karnezos Marcos (Menlo Park CA), Tab grid array.
  32. Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.

이 특허를 인용한 특허 (20)

  1. Searls, Damion T.; Dishongh, Terrance J.; Pullen, David, Apparatus and method for passive phase change thermal management.
  2. Searls, Damion T.; Dishongh, Terrance J.; Pullen, David, Apparatus and method for passive phase change thermal management.
  3. Suhir,Ephraim, Apparatus for attaching a cooling structure to an integrated circuit.
  4. Yamada, Yasuyoshi, Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board.
  5. Wu,Chung Ju; Lin,Wei Feng, Ball grid array package with heat sink device.
  6. West, David Justin; Russell, David John, Electrical contact alignment posts.
  7. West, David Justin; Russell, David John, Electrical contact alignment posts.
  8. Ichihara, Yasuhiro; Kogure, Seiji; Iimura, Hiroshi; Arase, Fumio, Electronic component package, printed circuit board, and method of inspecting the printed circuit board.
  9. So, Tsuyoshi, Electronic device, standoff member, and method of manufacturing electronic device.
  10. Weissbach, Ernst-A.; Ertl, Juergen, Flip-chip module and method for the production thereof.
  11. Rubenstein, Brandon A., Heat sink hold-down with fan-module attach location.
  12. Dangelo, Carlos; Olson, Darin, Integrated circuit micro-cooler having multi-layers of tubes of a CNT array.
  13. Suhir, Ephraim; Xu, Yuan; Zhang, Yi, Method and apparatus for evaluation and improvement of mechanical and thermal properties of CNT/CNF arrays.
  14. Deeney,Jeffrey L.; Dutson,Joseph D.; Luebs,Richard J., Method and apparatus for supporting a circuit component having solder column interconnects using an external support.
  15. Deeney, Jeffrey L.; Dutson, Joseph D.; Luebs, Richard J., Method and apparatus for supporting a circuit component having solder column interconnects using external support.
  16. Searls,Damion T.; Dishongh,Terrance J.; Pullen,David, Method for passive phase change thermal management.
  17. Odegard,Charles Anthony, System and method to increase die stand-off height.
  18. Dangelo, Carlos, System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler.
  19. Dangelo, Carlos; Spitzer, Jason, Vapor chamber heat sink having a carbon nanotube fluid interface.
  20. Delano,Andrew D.; Rubenstein,Brandon A.; Miksch,Eugene, Variable-gap thermal-interface device.
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