초록 ▼

A bridge device (12) in a computer system interconnects with peripheral component interconnect (PCI) devices (14) over a PCI bus (16). The bridge device (12) includes a plurality of read response buffers (10) to provide data to the PCI devices (14). Each of the read response buffers (10) has a plura

A bridge device (12) in a computer system interconnects with peripheral component interconnect (PCI) devices (14) over a PCI bus (16). The bridge device (12) includes a plurality of read response buffers (10) to provide data to the PCI devices (14). Each of the read response buffers (10) has a plurality of counters/registers (22) associated therewith. The counters/registers (22) measure various parameters associated with the request and retrieval of requested data and speculative data through the read response buffers (10). In response to the parameters measured by the counters/registers (22), the read response buffers (10) can be optimally allocated among the PCI devices (14).

대표청구항 ▼

1. A method of analyzing buffer allocation for a device on a peripheral component interconnect bus, comprising: receiving a request for data from the device; determining whether the data is present in a buffer group; retrieving the data from memory in response to the data not being present in the

1. A method of analyzing buffer allocation for a device on a peripheral component interconnect bus, comprising: receiving a request for data from the device; determining whether the data is present in a buffer group; retrieving the data from memory in response to the data not being present in the buffer group; issuing retry commands to the device until data is received in the buffer group, each retry command causing the device to re-request the data; receiving data in the buffer group from memory; transferring the data to the device; incrementing a first counter associated with a first buffer in the buffer group in response to a data transfer from the first buffer to the device; incrementing a second counter associated with the first buffer in response to the request being for data stored in a second buffer of the buffer group; periodically incrementing a third counter associated with the first buffer upon receiving the request until the data is received in the buffer group from the memory, the third counter determining a memory retrieval latency for the request.