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Copper interconnection structure incorporating a metal seed layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0714504 (2000-11-16)
발명자 / 주소
  • Daniel Charles Edelstein
  • James McKell Edwin Harper
  • Chao-Kun Hu
  • Andrew H. Simon
  • Cyprian Emeka Uzoh
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Robert M. Trepp
인용정보 피인용 횟수 : 45  인용 특허 : 18

초록 ▼

The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper c

대표청구항 ▼

1. A method for forming an interconnection structure for providing electrical connection to an electronic device comprising the steps of:depositing a copper alloy seed layer on an electronic device, and forming a copper conductor body on said copper alloy seed layer intimately bonding to said layer

이 특허에 인용된 특허 (18)

  1. Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL), Capped copper electrical interconnects.
    상세보기
  2. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
    상세보기
  3. Kato Masanori (Tokyo JPX), High-conductivity copper alloys with excellent workability and heat resistance.
    상세보기
  4. Crank Sue E. (Coppell TX), Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer.
    상세보기
  5. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel contai.
    상세보기
  6. Huang Chih-Kung,TWX ; Lai Wei-Jen,TWX, Leadframe for integrated circuit package.
    상세보기
  7. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
    상세보기
  8. Tao Jiang ; Fang Peng, Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity.
    상세보기
  9. Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL), Method for forming capped copper electrical interconnects.
    상세보기
  10. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
    상세보기
  11. Nogami Takeshi ; Dubin Valery ; Cheung Robin, Method of electroplating a copper or copper alloy interconnect.
    상세보기
  12. Pan Ju-Don T. (Austin TX), Method of making an electrical multilayer interconnect.
    상세보기
  13. Andricacos Panayotis Constantinou ; Deligianni Hariklia ; Harper James McKell Edwin ; Hu Chao-Kun ; Pearson Dale Jonathan ; Reynolds Scott Kevin ; Tu King-Ning ; Uzoh Cyprian Emeka, Method of making copper alloys for chip and package interconnections.
    상세보기
  14. Kwon Chul-soon,KRX, Methods of fabricating copper interconnects for integrated circuits.
    상세보기
  15. Kawai Michifumi,JPX ; Satoh Ryohei,JPX ; Yamada Osamu,JPX ; Matsuda Eiji,JPX ; Ishino Masakazu,JPX ; Inoue Takashi,JPX ; Sotokawa Hideo,JPX ; Kyoui Masayuki,JPX, Multilayer substrates methods for manufacturing multilayer substrates and electronic devices.
    상세보기
  16. Ting Chiu ; Dubin Valery, Plated copper interconnect structure.
    상세보기
  17. Zhang Jiming ; Denning Dean J., Process for forming a semiconductor device.
    상세보기
  18. Maniar Papu D. (Austin TX) Moazzami Reza (Austin TX) Mogab C. Joseph (Austin TX), Semiconductor device having a reducing/oxidizing conductive material.
    상세보기

이 특허를 인용한 특허 (45)

  1. Chung,Hua; Chen,Ling; Yu,Jick; Chang,Mei, Apparatus for integration of barrier layer and seed layer.
    상세보기
  2. Bao, Junjing; Bonilla, Griselda; Chanda, Kaushik; Choi, Samuel S.; Filippi, Ronald G.; Grunow, Stephan; Lustig, Naftali E.; Moy, Dan; Simon, Andrew H., Back-end electrically programmable fuse.
    상세보기
  3. Bao, Junjing; Bonilla, Griselda; Chanda, Kaushik; Choi, Samuel S.; Filippi, Ronald; Grunow, Stephan; Lustig, Naftali E.; Moy, Dan; Simon, Andrew H., Back-end electrically programmable fuse.
    상세보기
  4. Edelstein, Daniel C.; Nogami, Takeshi; Shobha, Hosadurga K., Barrier layer formation for metal interconnects through enhanced impurity diffusion.
    상세보기
  5. Edelstein, Daniel C.; Cooney, III, Edward C.; Fitzsimmons, John A.; Gambino, Jeffrey P.; Stamper, Anthony K., Copper alloy via bottom liner.
    상세보기
  6. Edelstein,Daniel C.; Cooney, III,Edward C.; Fitzsimmons,John A.; Gambino,Jeffrey P.; Stamper,Anthony K., Copper alloy via bottom liner.
    상세보기
  7. Lane,Michael W.; Chiras,Stefanie R.; Spooner,Terry A.; Rosenberg,Robert; Edelstein,Daniel C., Copper conductor.
    상세보기
  8. Mountsier, Thomas W.; Shaviv, Roey; Mayer, Steven T.; Powell, Ronald A., Diffusion barrier layers.
    상세보기
  9. Lin, Chun-Nan; Tu, Kuo-Yuan; Wu, Shu-Feng; Tsai, Wen-Ching, Display panel structure and manufacture method thereof.
    상세보기
  10. Dyer, Thomas W.; Edelstein, Daniel C.; Ko, Tze-man; Simon, Andrew H.; Tseng, Wei-tsu, Doping of copper wiring structures in back end of line processing.
    상세보기
  11. Yang, Chih-Chao; Edelstein, Daniel C.; Nogami, Takeshi, Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application.
    상세보기
  12. Yang, Chih-Chao; Edelstein, Daniel C.; Nogami, Takeshi, Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application.
    상세보기
  13. Faust, Richard A.; Jiang, Qing-Tang; Lu, Jiong-Ping, In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliability.
    상세보기
  14. Nag, Joyeeta; Ray, Shishir K.; Simon, Andrew H.; Gluschenkov, Oleg; Krishnan, Siddarth A.; Chudzik, Michael P., Integrated circuit having improved electromigration performance and method of forming same.
    상세보기
  15. Wang, Pin-Chin Connie; Avanzino, Steven C., Integrated circuit with low solubility metal-conductor interconnect cap.
    상세보기
  16. Chung,Hua; Chen,Ling; Yu,Jick; Chang,Mei, Integration of barrier layer and seed layer.
    상세보기
  17. Simka, Harsono S.; Zierath, Daniel J.; Haverty, Michael G.; Shankar, Sadasivan, Liner layers for metal interconnects.
    상세보기
  18. Lane,Michael; Chiras,Stefanie R.; Spooner,Terry A.; Rosenberg,Robert; Edelstein,Daniel C., Metal capped copper interconnect.
    상세보기
  19. Lopatin, Sergey D.; Besser, Paul R.; Buynoski, Matthew S.; Wang, Pin-Chin Connie, Method of forming an adhesion layer with an element reactive with a barrier layer.
    상세보기
  20. Lopatin, Sergey D.; Besser, Paul R.; Buynoski, Matthew S., Method of implantation after copper seed deposition.
    상세보기
  21. Besser, Paul R.; Buynoski, Matthew S.; Lopatin, Sergey D., Method of implanting copper barrier material to improve electrical performance.
    상세보기
  22. Besser, Paul R.; Buynoski, Matthew S.; Lopatin, Sergey D.; Myers, Alline F.; Wang, Phin-Chin Connie, Method of inserting alloy elements to reduce copper diffusion and bulk diffusion.
    상세보기
  23. Lopatin,Sergey D.; Besser,Paul R.; Myers,Alline F.; Romero,Jeremias D.; Tran,Minh Q.; You,Lu; Wang,Pin Chin Connie, Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition.
    상세보기
  24. Lopatin, Sergey D.; Besser, Paul R.; Wang, Pin-Chin Connie, Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect.
    상세보기
  25. Kim, Hoon; Lee, Wei Ti; Yu, Sang Ho; Ganguli, Seshadri; Ha, Hyoung-Chan; Lee, Sang Hyeob, Methods for forming barrier/seed layers for copper interconnect structures.
    상세보기
  26. Yoon, Hyungsuk Alexander; Redecker, Fritz, Methods of fabricating electronic devices using direct copper plating.
    상세보기
  27. Bruley,John; Carruthers,Roy A.; Gignac,Lynne Marie; Hu,Chao Kun; Liniger,Eric Gerhard; Malhotra,Sandra Guy; Rossnagel,Stephen M., On-chip Cu interconnection using 1 to 5 nm thick metal cap.
    상세보기
  28. Wai,Chien M.; Ohde,Hiroyuki; Kramer,Steve, Semiconductor constructions.
    상세보기
  29. Wai,Chien M.; Ohde,Hiroyuki; Kramer,Steve, Semiconductor constructions comprising a layer of metal over a substrate.
    상세보기
  30. Jang, Sung Ho, Semiconductor device and method of forming metal interconnection layer thereof.
    상세보기
  31. Amishiro, Hiroyuki; Igarashi, Motoshige, Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method.
    상세보기
  32. Amishiro, Hiroyuki; Igarashi, Motoshige, Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method.
    상세보기
  33. Ueno, Kazuyoshi, Semiconductor device with improved stress migration resistance and manufacturing process therefor.
    상세보기
  34. Iwasaki, Tomio; Miura, Hideo; Asano, Isamu, Semiconductor device with multilayer conductive structure formed on a semiconductor substrate.
    상세보기
  35. Iwasaki,Tomio; Miura,Hideo; Asano,Isamu, Semiconductor device with multilayer conductive structure formed on a semiconductor substrate.
    상세보기
  36. Kuzuhara, Takeshi; Komura, Atsushi; Katada, Mitsutaka; Naruse, Takayoshi, Semiconductor device, wiring of semiconductor device, and method of forming wiring.
    상세보기
  37. Cabral, Jr., Cyril; Dubois, Geraud J. M.; Edelstein, Daniel C.; Nogami, Takeshi; Sanders, Daniel P., Semiconductor interconnect structure having enhanced performance and reliability.
    상세보기
  38. Cabral, Jr., Cyril; Dubois, Geraud Jean-Michel; Edelstein, Daniel C.; Nogami, Takeshi; Sanders, Daniel P., Semiconductor interconnect structure having enhanced performance and reliability.
    상세보기
  39. Edelstein, Daniel C; Nogami, Takeshi, Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration.
    상세보기
  40. Roberds, Brian; Barlage, Doulgas W., Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering.
    상세보기
  41. Roberds, Brian; Barlage, Doulgas W., Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering.
    상세보기
  42. Baik, Chan Wook; Kim, Jong Seok; Kim, Sun Il; Son, Young Mok, Substrate structure and method of forming the same.
    상세보기
  43. Mori, Satoru; Komiyama, Shozo, Thin-film transistor and intermediate of thin-film transistor.
    상세보기
  44. Mori, Satoru; Komiyama, Shozo, Thin-film transistor having high adhesive strength between barrier film and drain electrode and source electrode films.
    상세보기
  45. Achuthan, Krishnashree; Lopatin, Sergey, Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure.
    상세보기

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