초록 ▼

A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip.

A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

대표청구항 ▼

1. A CTE compensated semiconductor chip interposer comprising:a first layer of high elastic modulus dielectric material having a low CTE; a second layer of dielectric material with metallurgy formed thereon having a lower elastic modulus than the elastic modulus of said first layer of material and h

1. A CTE compensated semiconductor chip interposer comprising:a first layer of high elastic modulus dielectric material having a low CTE; a second layer of dielectric material with metallurgy formed thereon having a lower elastic modulus than the elastic modulus of said first layer of material and having a higher composite CTE than the CTE said of first layer of material; and a third layer of dielectric material with metallurgy formed thereon having a composite CTE between the CTEs of said first and second layers of dielectric material, said third layer of dielectric material laminated between said first layer of dielectric material and said second layer of dielectric material to form a multilayer interposer having formed therein an array of conductive vias extending therethrough.