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Configurable lookup table for programmable logic devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-025/00
출원번호 US-0861261 (2001-05-18)
발명자 / 주소
  • Ralph D. Wittig
  • Sundararajarao Mohan
  • Bernard J. New
출원인 / 주소
  • Xilinix, Inc.
대리인 / 주소
    Lois D. Cartier
인용정보 피인용 횟수 : 55  인용 특허 : 9

초록

A configurable logic element (CLE) for a field programmable gate array (FPGA) includes "expanders", i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logic

대표청구항

1. A configurable logic element (CLE) for a programmable logic device (PLD), the CLE comprising:a logic block providing two N-input lookup tables (LUTS), the logic block having a first LUT mode wherein the two LUTs have at least one unshared input and a second LUT mode wherein the two LUTs have N sh

이 특허에 인용된 특허 (9)

  1. Carter William S. (Santa Clara CA), Configurable logic element.
  2. Freeman Ross H. (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA), Distributed memory architecture for a configurable logic array and method for using distribution memory.
  3. Chiang David (Saratoga CA), EPLD chip with hybrid architecture optimized for both speed and flexibility.
  4. Kean Thomas A.,GB6, Embedded memory for field programmable gate array.
  5. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  6. Freidin Philip M. (Sunnyvale CA), Logic block with look-up table for configuration and memory.
  7. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.
  8. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron ; Leong William ; Watson James Allen ; Huang Joseph ; Ahanin Bahram ; Sung Chiakang ; Chang Wanli, Programmable logic array integrated circuits.
  9. Stansfield Anthony I. (Hotwells GBX), Programmable logic device with memory that can store routing data of logic data.

이 특허를 인용한 특허 (55)

  1. Lewis,David; Pedersen,Bruce; Kaptanoglu,Sinan, Arithmetic structures for programmable logic devices.
  2. Logue, John D.; Ching, Alvin Y.; Lu, Wei Guang, Automatic tap delay calibration for precise digital phase shift.
  3. Young,Steven P., Columnar architecture.
  4. Young, Steven P., Columnar floorplan.
  5. Vadi, Vasisht Mantra; Young, Steven P.; Ghia, Atul V.; Bekele, Adebabay M.; Menon, Suresh M., Differential clock tree in an integrated circuit.
  6. Morrison,Shawn K.; Pang,Raymond C., Digital clock manager capacitive trim unit.
  7. Pang,Raymond C.; Wong,Jennifer, Digital clock manager having cascade voltage switch logic clock paths.
  8. Pugh, Daniel J.; Fox, Andrew W.; Wong, Dale, Field programmable gate array core cell with efficient logic packing.
  9. Bauer,Trevor J.; Young,Steven P., Formation of columnar application specific circuitry using a columnar programmable logic device.
  10. Kaptanoglu,Sinan; Lewis,David; Pedersen,Bruce, Fracturable incomplete look up table area efficient logic elements.
  11. Kaptanoglu, Sinan; Lewis, David; Pedersen, Bruce, Fracturable incomplete look up table for area efficient logic elements.
  12. Lewis, David; Pedersen, Bruce; Kaptanoglu, Sinan; Lee, Andy, Fracturable lookup table and logic element.
  13. Lewis, David; Pedersen, Bruce; Kaptanoglu, Sinan; Lee, Andy, Fracturable lookup table and logic element.
  14. Lewis, David; Pedersen, Bruce; Kaptanoglu, Sinan; Lee, Andy L., Fracturable lookup table and logic element.
  15. Lewis,David; Pedersen,Bruce; Kaptanoglu,Sinan; Lee,Andy, Fracturable lookup table and logic element.
  16. Lewis,David; Pedersen,Bruce; Kaptanoglu,Sinan; Lee,Andy L., Fracturable lookup table and logic element.
  17. Chirania,Manoj, Integrated circuit including a multiplexer circuit.
  18. Lewis,David; Schleicher,James, LUT-based logic element with support for Shannon decomposition and associated method.
  19. Baeckler, Gregg; Langhammer, Martin; Schleicher, James; Yuan, Richard, Logic cell supporting addition of three binary words.
  20. Pedersen, Bruce, Logic circuitry with shared lookup table.
  21. Pedersen,Bruce, Logic circuitry with shared lookup table.
  22. Claseman,George R., Look-up table expansion method.
  23. Chirania,Manoj; Kondapalli,Venu M., Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs.
  24. Chirania,Manoj, Lookup table with relatively balanced delays.
  25. Brissenden, Scott James; McHardy, Paul, Method and apparatus for automatic hierarchical design partitioning.
  26. Brissenden, Scott James; McHardy, Paul, Method and apparatus for automatic hierarchical design partitioning.
  27. New, Bernard J., Method and apparatus for communicating data between stacked integrated circuits.
  28. Schleicher, II,James G; Yuan,Jinyong, Methods for producing equivalent logic designs for FPGAs and structured ASIC devices.
  29. Simkins,James M., Methods of setting and resetting lookup table memory cells.
  30. Schleicher, James; Yuan, Richard; Pedersen, Bruce; Kaptanoglu, Sinan; Baeckler, Gregg; Lewis, David; Hutton, Michael; Lee, Andy; Saini, Rahul; Kim, Henry, Omnibus logic element.
  31. Schleicher, James; Yuan, Richard; Pedersen, Bruce; Kaptanoglu, Sinan; Baeckler, Gregg; Lewis, David; Hutton, Mike; Lee, Andy L.; Saini, Rahul; Kim, Henry, Omnibus logic element.
  32. Schleicher, James; Yuan, Richard; Pedersen, Bruce; Kaptanoglu, Sinan; Baeckler, Gregg; Lewis, David; Hutton, Mike; Lee, Andy L.; Saini, Rahul; Kim, Henry, Omnibus logic element.
  33. Schleicher, James; Yuan, Richard; Pedersen, Bruce; Kaptanoglu, Sinan; Baeckler, Gregg; Lewis, David; Hutton, Mike; Lee, Andy L.; Saini, Rahul; Kim, Henry, Omnibus logic element.
  34. Schleicher, James; Yuan, Richard; Pedersen, Bruce; Kaptanoglu, Sinan; Baeckler, Gregg; Lewis, David; Hutton, Mike; Lee, Andy; Saini, Rahul; Kim, Henry, Omnibus logic element for packing or fracturing.
  35. Schleicher, James; Yuan, Richard; Pedersen, Bruce; Kaptanoglu, Sinan; Baeckler, Gregg; Lewis, David; Hutton, Mike; Lee, Andy; Saini, Rahul; Kim, Henry, Omnibus logic element for packing or fracturing.
  36. Ganesan, Satish R.; Kasat, Amit, PLD configurable logic block enabling the rapid calculation of sum-of-products functions.
  37. Percey,Andrew K.; Pang,Raymond C., Phase matched clock divider.
  38. Young,Steven P.; Bauer,Trevor J., Programmable integrated circuit providing efficient implementations of arithmetic functions.
  39. Young,Steven P., Programmable integrated circuit providing efficient implementations of wide logic functions.
  40. Kondapalli,Venu M.; Chirania,Manoj, Programmable logic block having improved performance when functioning in shift register mode.
  41. Young,Steven P., Programmable logic block having lookup table with partial output signal driving carry multiplexer.
  42. Chirania, Manoj; Kondapalli, Venu M., Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode.
  43. Young,Steven P.; Bauer,Trevor J.; Chirania,Manoj; Kondapalli,Venu M., Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure.
  44. Kurokawa, Yoshiyuki; Ikeda, Takayuki, Programmable logic device.
  45. Lewis,David; Cashman,David, Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks.
  46. Lewis,David; Cashman,David, Programmable logic device having redundancy with logic element granularity.
  47. Kondapalli,Venu M.; Bauer,Trevor J.; Chirania,Manoj; Costello,Philip D.; Young,Steven P., Programmable lookup table with dual input and output terminals in RAM mode.
  48. Kondapalli,Venu M.; Bauer,Trevor J.; Chirania,Manoj; Costello,Philip D.; Young,Steven P., Programmable lookup table with dual input and output terminals in shift register mode.
  49. Jang,Tetse; Zhou,Shi dong, Scalable complex programmable logic device with segmented interconnect resources.
  50. Young,Steven P.; Kondapalli,Venu M.; Tanikella,Ramakrishna K., Six-input look-up table and associated memory control circuitry for use in a field programmable gate array.
  51. Young,Steven P.; Kondapalli,Venu M.; Tanikella,Ramakrishna K., Six-input look-up table for use in a field programmable gate array.
  52. Lewis, David M.; Leventis, Paul; Lee, Andy L.; Kim, Henry; Pedersen, Bruce; Wysocki, Chris; Lane, Christopher F.; Marquardt, Alexander; Santurkar, Vikram; Betz, Vaughn, Versatile logic element and logic array block.
  53. Lewis, David M.; Leventis, Paul; Lee, Andy L.; Kim, Henry; Pedersen, Bruce; Wysocki, Chris; Lane, Christopher F.; Marquardt, Alexander; Santurkar, Vikram; Betz, Vaughn, Versatile logic element and logic array block.
  54. Lewis,David M.; Leventis,Paul; Lee,Andy L.; Kim,Henry; Pedersen,Bruce; Wysocki,Chris; Lane,Christopher F.; Marquardt,Alexander; Santurkar,Vikram; Betz,Vaughn, Versatile logic element and logic array block.
  55. Lewis,David M.; Leventis,Paul; Lee,Andy L.; Kim,Henry; Pedersen,Bruce; Wysocki,Chris; Lane,Christopher F.; Marquardt,Alexander; Santurkar,Vikram; Betz,Vaughn Timothy, Versatile logic element and logic array block.
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