초록 ▼

A mechanism and method for software hint initiated prefetch is provided. The prefetch may be directed to a prefetch of data for loading into a data cache, instructions for entry into an instruction cache or for either, in an embodiment having a combined cache. In response to a software instruction i

A mechanism and method for software hint initiated prefetch is provided. The prefetch may be directed to a prefetch of data for loading into a data cache, instructions for entry into an instruction cache or for either, in an embodiment having a combined cache. In response to a software instruction in an instruction stream, a plurality of prefetch specification data values are loaded into a register having a plurality of entries corresponding thereto. Prefetch specification data values include the address of the first cache line to be prefetched, and the stride, or the incremental offset, of the address of subsequent lines to be prefetched. Prefetch requests are generated by a prefetch control state machine using the prefetch specification data values stored in the register. Prefetch requests are issued to a hierarchy of cache memory devices. If a cache hit occurs having the specified cache coherency, the prefetch is vitiated. Otherwise, the request is passed to system memory for retrieval of the requested cache line.

대표청구항 ▼

1. An apparatus for software hint initiated prefetch comprising:circuitry operable for issuing at least one prefetch request to one or more memory devices in response to a software instruction, said circuitry including at least one first register having a plurality of fields each operable for receiv

1. An apparatus for software hint initiated prefetch comprising:circuitry operable for issuing at least one prefetch request to one or more memory devices in response to a software instruction, said circuitry including at least one first register having a plurality of fields each operable for receiving a corresponding data value, each data value specifying a parameter for controlling said prefetch, wherein said circuitry comprises at least one prefetch engine, each prefetch engine being operable for issuing one of said at least one prefetch request, each said prefetch engine including one of said at least one first register, and wherein each prefetch engine further comprises a prefetch control state machine, wherein in each prefetch engine further comprises circuitry operable for detecting an end of prefetch, and wherein in said circuitry operable for detecting an end of prefetch comprises: a second register operable for containing a count representing a number of cache lines currently prefetched, said second register being operable for resetting by said prefetched control state machine; comparison logic coupled to said second register operable for receiving therefrom said number of cache lines currently prefetched, said comparison logic being operable for receiving a number of cache lines to be prefetched from said first register, wherein said comparison logic outputs a prefetch done signal if said number of cache lines currently prefetched equals said number of cache lines to be prefetched; and incrementing circuitry operable for incrementing said number of cache lines currently prefetched, said incrementing circuitry being operable for inputting an incremented number of cache lines into said second register.