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Circuit encapsulation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B29C-045/02
  • B29C-045/14
출원번호 US-0337581 (1999-06-22)
발명자 / 주소
  • John R. Saxelby, Jr.
  • Walter R. Hedlund, III
출원인 / 주소
  • VLT Corporation
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 29  인용 특허 : 42

초록

A circuit on a circuit board is encapsulated using a first mold section and a second mold section. The first mold section closes on one side of the board, and the first mold section has an exposed first conduit. The second mold section closes on another side of the board, and the second mold section

대표청구항

1. A method for encapsulating a circuit on a circuit board, comprising:closing a first mold section on one side of the board, the first mold section having an exposed cylinder; closing a second mold section on another side of the board, the second mold section having a conduit for pushing molding co

이 특허에 인용된 특허 (42)

  1. Chou C. H. (Taipei TWX) Wang T. H. (Taipei Hsien TWX) Chen C. S. (Taipei Hsien TWX), Air exhaust mold plunger.
  2. Moitzger Max (Lodi CA), Apparatus for encapsulating selected portions of a printed circuit board.
  3. De\Ath Roderick M. (Oxfordshire GB2), Apparatus for injection moulding.
  4. Shaheen Joseph M. (La Habra CA), Ceramic/organic multilayer interconnection board.
  5. Derryberry Lesli A. (Dallas TX) Williams Charles E. (Dallas TX), Circuit board with a chip carrier and mounting structure connected to the chip carrier.
  6. Leatham James G. (Redondo Beach CA), Circuit package attachment apparatus and method.
  7. Kaufman Lance R. (131 White Oak Way Mequon WI 53092), Compact circuit package having improved circuit connectors.
  8. Fierkens Richard H. J. (Keurbeck 15 6914 Ae Herwen NLX), Compression-cavity mold for plastic encapsulation of thin-package integrated circuit device.
  9. Bartley John E. (Greenfield WI) Penrod Orville R. (Kernersville NC), Edge termination for an electrical circuit device.
  10. Yamamoto Masato (Imari JPX), Electric device with an operation indicating lamp.
  11. Knoll Carl G. (Melrose Park IL), Electrical terminal constructed to prevent insert molding flash.
  12. Baird John (Scottsdale AZ), Encapsulation means and method for reducing flash.
  13. Neugebauer Constantine A. (Schenectady NY) Satriano Robert J. (Hackettstown NJ) Burgess James F. (Schenectady NY) Glascock ; II Homer H. (Scotia NY) Temple Victor A. K. (Clifton Park NY) Watrous Dona, High current hermetic package having a lead extending through the package lid and a packaged semiconductor chip.
  14. Wojnarowski Robert J. (Ballston Lake NY) Eichelberger Charles W. (Schenectady NY) Kornrumpf William P. (Albany NY), High density interconnect structure including a chamber.
  15. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY), High density interconnect with high volumetric efficiency.
  16. Boucard Michel (Tournefeuille FRX) Thirion Christian (Auterive FRX) Maurel Christian (Toulouse FRX), Housing for an electronic circuit.
  17. Werther William E. (Glen Cove NY), Interconnection package suitable for electronic devices and methods for producing same.
  18. Gilbert, Barry K.; Schwab, Daniel J., Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation.
  19. Gilbert, Barry K.; Schwab, Daniel J., Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation.
  20. Benenati Robert (Tamarac FL) Desjardins Joseph (Tamarac FL) Mitzlaff James E. (Carpentersville IL) Beutler Scott D. (Des Plaines IL) Albert Mike M. (Chicago IL) Brown Vernon L. (Barrington IL), Leadless chip carrier for RF power transistors or the like.
  21. Kaufman Lance R. (131 N. White Oak Way Mequon WI 53092), Low cost compressively clamped circuit and heat sink assembly.
  22. Hamada Makoto (Tokyo JPX) Ise Hiroshi (Tokyo JPX), Metal mold for sealing semiconductor devices with a resin.
  23. McShane Michael B. (Austin TX) Woosley Alan H. (Austin TX) Primeaux Francis (Austin TX), Method for encapsulating semiconductor devices with package bodies.
  24. Goo Lee (Seoul KRX), Method for molding of integrated circuit package.
  25. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY) Welles ; II Kenneth B. (Schenectady NY), Method for packaging integrated circuit chips employing a polymer film overlay layer.
  26. Heft Josef (Munich DEX), Method for producing electrical connection with a ribbon cable.
  27. Leeb Karl-Erik (Djurhamn SEX), Method of manufacturing circuit board having lateral conductive pattern.
  28. Arai Yasunari (Tokyo JPX) Hamano Hiroshi (Kawasaki JPX) Amemiya Izumi (Yokohama JPX) Yamamoto Takuji (Kawasaki JPX) Ihara Takeshi (Kawasaki JPX), Method of producing an electronic circuit package.
  29. Chia Chok J. (Santa Clara CA), Molded pin grid array package GPT.
  30. Sakai Kunito (Hyogo JPX) Oshio Kazuharu (Hyogo JPX) Kanegae Hirozoh (Hyogo JPX), Molding machine and method.
  31. Wolf Franz-Josef (Bad Soden Salmunster DEX), Molding tool.
  32. Shimada Yuzo (Tokyo JPX) Kurokawa Yasuhiro (Tokyo JPX) Utsumi Kazuaki (Tokyo JPX), Multi-layer circuit board having a large heat dissipation.
  33. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY), Multichip integrated circuit packaging configuration and method.
  34. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY), Multichip integrated circuit packaging method.
  35. Kaufman, Lance R., Multiple substrate circuit package.
  36. Vinciarelli Patrizio (Boston MA) Finnemore Fred (No. Reading MA) Balog John S. (Mendon MA) Johnson Brant T. (Concord MA), Packaging electrical components.
  37. Carlson Randolph S. (Carson City NV) Chase Charles P. (Carson City NV), Packaging system for stacking integrated circuits.
  38. Chia Chok J. (Santa Clara CA), Plastic molded pin-grid-array power package.
  39. Morris James B. (Bloomington MN), Process for assembling integrated circuit packages.
  40. Konishi Akira (Kyoto JPX) Wakano Teruo (Kyoto JPX), Semiconductor device and its manufacture.
  41. Mennitt Timothy J. (Cedar Park TX) Warren John P. (Austin TX) Sloan James W. (Austin TX), Semiconductor device with test-only contacts and method for making the same.
  42. Calver John G. (Rochester NY) Pearce Phillip W. (Pavilion NY) Zielinski Erich (Bergen NY), Semiconductor mounting assembly.

이 특허를 인용한 특허 (29)

  1. Karmazyn, Michael J., Angular encapsulation of tandem stacked printed circuit boards.
  2. Vinciarelli, Patrizio; LaFleur, Michael B.; Fleming, Sean Timothy; Mutter, Rudolph F.; D'Amico, Andrew T., Encapsulated modular power converter with symmetric heat distribution.
  3. Vinciarelli, Patrizio, Encapsulation method and apparatus for electronic modules.
  4. Vinciarelli, Patrizio; LaFleur, Michael B., Encapsulation method and apparatus for electronic modules.
  5. Vinciarelli, Patrizio; LaFleur, Michael B., Encapsulation method for electronic modules.
  6. Mori,Haruhiko; Kanakubo,Masaru; Sakamoto,Hideyuki, Hybrid integrated circuit device and method of manufacturing the same.
  7. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  8. Ahmad,Syed Sajid, Interconnecting substrates for electrical coupling of microelectronic components.
  9. Low, Jeffrey Khai Huat; Lee, Kean Cheong, Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component.
  10. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  11. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  12. Bolken, Todd O., Method and apparatus for packaging a microelectronic die.
  13. Ahmad, Syed Sajid, Method of Interconnecting substrates for electrical coupling of microelectronic components.
  14. Vinciarelli, Patrizio; Lavery, Patrick R.; Mutter, Rudolph F.; Kirk, Jeffery J.; D'Amico, Andrew T., Method of electrically interconnecting circuit assemblies.
  15. Cobbley,Chad A., Method of encapsulating interconnecting units in packaged microelectronic devices.
  16. Cobbley,Chad A., Method of encapsulating packaged microelectronic devices with a barrier.
  17. Vinciarelli, Patrizio; Balcius, Robert Joseph; Sadler, Steven P.; Thompson, Mark Andrew, Method of forming an electrical connection to an electronic module.
  18. Vinciarelli, Patrizio; Lafleur, Michael B.; Fleming, Sean Timothy; Mutter, Rudolph; D'Amico, Andrew T., Method of forming an electrical contact.
  19. Vinciarelli, Patrizio; LaFleur, Michael B.; Fleming, Sean Timothy; Mutter, Rudolph F.; D'Amico, Andrew T., Method of making a plurality of electronic assemblies.
  20. Bolken, Todd O., Microelectronic devices and microelectronic die packages.
  21. Cobbley, Chad A., Packaged microelectronic devices with interconnecting units.
  22. James, Stephen L.; Cobbley, Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  23. James,Stephen L.; Cobbley,Chad A., Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices.
  24. Vinciarelli, Patrizio; LaFleur, Michael B.; Fleming, Sean Timothy; Mutter, Rudolph F.; D'Amico, Andrew T., Panel-molded electronic assemblies.
  25. Vinciarelli, Patrizio, Power adapter packaging.
  26. Vinciarelli, Patrizio; LaFleur, Michael B.; McCauley, Charles I.; Starenas, Paul V., Power converter package and thermal management.
  27. Vinciarelli,Patrizio; Lafleur,Michael B.; McCauley,Charles I.; Starenas,Paul V., Power converter package and thermal management.
  28. Vinciarelli, Patrizio; Lafleur, Michael B., System and apparatus for efficient heat removal from heat-generating electronic modules.
  29. Farnworth, Warren M., Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece.
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