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Semiconductor device, and operating device, signal converter, and signal processing system using the same semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
출원번호 US-0548545 (1995-10-26)
우선권정보 JP-0265039 (1994-10-28)
발명자 / 주소
  • Shunsuke Inoue JP
  • Mamoru Miyawaki JP
  • Tetsunobu Kochi JP
출원인 / 주소
  • Canon Kabushiki Kaisha JP
대리인 / 주소
    Fitzpatrick, Cella, Harper & Scinto
인용정보 피인용 횟수 : 84  인용 특허 : 7

초록

In a semiconductor device which has capacitors respectively connected to multiple input terminals, and in which the remaining terminals of the capacitors are commonly connected to a sense amplifier, the capacitors and the sense amplifier are formed by utilizing a semiconductor layer on an insulating

대표청구항

1. A semiconductor device comprising:a plurality of input terminals capable of inputting signals independently of each other; a capacitor that includes a plurality of capacitor elements each with two opposed electrodes, a first of the two electrodes being electrically connected to one of the plurali

이 특허에 인용된 특허 (7)

  1. Larson Lawrence E. (Los Angeles CA) Jensen Joseph F. (Malibu CA) Walden Robert H. (Westlake Village CA) Schmitz Adele E. (Newbury Park CA), Analog-to-digital converter made with focused ion beam technology.
  2. Cameron Frank L. (Wellesley Hills MA), Charge redistribution circuits.
  3. Cade Paul Edmand (Milton VT), Depletion mode field effect transistor memory system.
  4. Buerger ; Jr. Walter R. (20769 Mesarica Rd. Covina CA 91724), Semi-monolithic memory with high-density cell configurations.
  5. Kikuchi Shin (Isehara JPX) Miyawaki Mamoru (Tokyo JPX) Monma Genzo (Hiratsuka JPX) Ohzu Hayao (Kawasaki JPX) Inoue Shunsuke (Yokohama JPX) Nakamura Yoshio (Atsugi JPX) Ichikawa Takeshi (Zama JPX) Ike, Semiconductor device and method of manufacturing the same.
  6. Yuzurihara Hiroshi (Isehara JPX) Miyawaki Mamoru (Tokyo JPX) Ishizaki Akira (Atsugi JPX) Momma Genzo (Hiratsuka JPX) Kochi Tetsunobu (Hiratsuka JPX), Semiconductor device having an insulated gate transistor.
  7. Hu Chenming (Alamo CA) Chan Mansun J. (Fremont CA) Wann Hsing-Jen (Albany CA) Ko Ping K. (Richmond CA), Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibil.

이 특허를 인용한 특허 (84)

  1. Glasper,John L; Robbins,David J; Leong,Weng Y, Avalanche photodiode with reduced sidewall defects.
  2. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  3. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  5. El-Kareh, Badih, Buried decoupling capacitors, devices and systems including same, and methods of fabrication.
  6. El-Kareh, Badih, Buried decoupling capacitors, devices and systems including same, and methods of fabrication.
  7. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  8. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  9. Datta, Suman; Hudait, Mantu K.; Doczy, Mark L.; Kavalieros, Jack T.; Amian, Majumdar; Brask, Justin K.; Jin, Been-Yih; Metz, Matthew V.; Chau, Robert S., Extreme high mobility CMOS logic.
  10. Datta, Suman; Hudait, Mantu K.; Doczy, Mark L.; Kavalieros, Jack T.; Amian, Majumdar; Brask, Justin K.; Jin, Been-Yih; Metz, Matthew V.; Chau, Robert S., Extreme high mobility CMOS logic.
  11. Datta, Suman; Hudait, Mantu K.; Doczy, Mark L.; Kavalieros, Jack T.; Amian, Majumdar; Brask, Justin K.; Jin, Been-Yih; Metz, Matthew V.; Chau, Robert S., Extreme high mobility CMOS logic.
  12. Datta, Suman; Hudait, Mantu K.; Doczy, Mark L.; Kavalieros, Jack T.; Majumdar, Amlan; Brask, Justin K.; Jin, Been-Yih; Metz, Matthew V.; Chau, Robert S., Extreme high mobility CMOS logic.
  13. Datta, Suman; Hudait, Mantu K.; Doczy, Mark L.; Kavalieros, Jack T.; Majumdar, Amlan; Brask, Justin K.; Jin, Been-Yih; Metz, Matthew V.; Chau, Robert S., Extreme high mobility CMOS logic.
  14. Datt{dot over (a)}, Suman; Hudait, Mantu K.; Doczy, Mark L.; Kavalieros, Jack T.; Amlan, Majumdar; Brask, Justin K.; Jin, Been-Yih; Metz, Matthew V.; Chau, Robert S., Extreme high mobility CMOS logic.
  15. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  19. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  20. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  21. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  22. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  23. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  24. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  25. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  26. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  27. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  28. Fried,David M.; Nowak,Edward J., Integrated circuit with capacitors having a fin structure.
  29. DeForge, John B.; Ellis-Monaghan, John J.; Hook, Terence B.; Peterson, Kirk D., Lateral non-volatile storage cell.
  30. DeForge, John B.; Ellis-Monaghan, John J.; Hook, Terence B.; Peterson, Kirk D., Lateral non-volatile storage cell.
  31. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
  32. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  33. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  34. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  35. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  36. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  37. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  38. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  39. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  40. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  41. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  42. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  43. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  44. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  45. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  46. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  47. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  48. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  49. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  50. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  51. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  52. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  53. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  54. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  55. Marshall, Gillian F; Robbins, David J; Leong, Wang Y; Birch, Steven W, Photodetector circuit.
  56. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  57. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  58. Ishikawa,Akira, Semiconductor device and method for preparing the same.
  59. Ishikawa, Akira, Semiconductor device having a buffer layer against stress.
  60. Ishikawa, Akira, Semiconductor device including a thin film transistor and a capacitor.
  61. Ishikawa, Akira, Semiconductor device including a thin film transistor and capacitor.
  62. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  63. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  64. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  65. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  66. Huang, Chyi-Chyuan; Lin, Shyh-An; Hsu, Chen-Fu, Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof.
  67. Huang, Chyi-Chyuan; Lin, Shyh-An; Hsu, Chen-Fu, Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof.
  68. El-Kareh, Badih, Semiconductor-on-insulator apparatus, device and system with buried decoupling capacitors.
  69. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  70. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  71. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  72. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  73. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  74. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  75. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  76. Aggrawal, Himanshu; Babakhani, Aydin, Systems and methods for active cancellation for improving isolation of transmission gates in high-frequency analog to digital converters.
  77. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
  78. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  79. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  80. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  81. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  82. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  83. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  84. Chau,Robert; Datta,Suman; Doyle,Brian S; Jin,Been Yih, Tri-gate transistors and methods to fabricate same.
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