초록 ▼

In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a res

In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a respective test memory cell at the far end of each respective bit line relative to its bit line driver. An intra-layer short between word lines may be detected, such as during manufacturing testing, by biasing adjacent word lines to different voltages and detecting whether any leakage current flowing from one to another exceeds that normally accounted for by the memory cells and other known circuits. Intra-layer bit line shorts and inter-layer word line and bit line shorts may also be similarly detected. An "open" in a word line or bit line may be detected by trying to program the test memory cell at the far end of each such word line or bit line. If successfully programmed, the continuity of each word line and bit line is assured, and the programming circuitry for each word line and bit line is also known to be functional.

대표청구항 ▼

1. In an integrated circuit including a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of:providing at least one test word line and at least

1. In an integrated circuit including a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of:providing at least one test word line and at least one test bit line for the array; providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, to ascertain at least one characteristic of the test memory cells; and using the at least one ascertained characteristic of the test memory cells to predict whether related memory cells in the array will program correctly.