$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Cache fencing for interpretive environments 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
출원번호 US-0705370 (2000-11-03)
발명자 / 주소
  • Phillip M. Adams
출원인 / 주소
  • Novell, Inc.
대리인 / 주소
    Haynes and Boone, LLP
인용정보 피인용 횟수 : 8  인용 특허 : 30

초록

An apparatus and method for cache fencing allows programmatic control of the access and duration of stay of selected executables within processor cache. In one example, an instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded im

대표청구항

1. A memory device comprising data structures storing executables for executing by a processor operably connected to the memory device and a processor cache, the data structures comprising:an operating system structure containing an operating system having a scheduler; a pin manager structure contai

이 특허에 인용된 특허 (30)

  1. Adams Phillip M., Accelerator for interpretive environments.
  2. Sites Richard Lee (Menlo Park CA), Alternate execution and interpretation of computer program having code at unknown locations due to transfer instructions.
  3. Adams Phillip M., Burst-loading of instructions into processor cache by execution of linked jump instructions embedded in cache line size blocks.
  4. Asghar Saf ; Ireton Mark ; Bartkowiak John, CPU with DSP having decoder that detects and converts instruction sequences intended to perform DSP function into DSP f.
  5. Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don, Cache block store instruction operations where cache coherency is achieved without writing all the way back to main mem.
  6. Ghori Amar A. (El Dorado Hills CA) Gavish Dan (Haifa ILX), Cache coherency maintenance of non-cache supporting buses.
  7. Edmondson John H. (Cambridge MA) Biro Larry L. (Oakham MA), Combined write-operand queue and read-after-write dependency scoreboard.
  8. Kummer David A. (Thousand Oaks CA) Rumer Robert T. (Camarillo CA), Computer system including a write protection circuit for preventing illegal write operations and a write poster with imp.
  9. Correnti Joseph A. (Boca Raton FL) Pipitone Ralph M. (Boynton Beach FL) Thomas Michael W. (Bellevue WA), Data processing system and method having selectable scheduler.
  10. Jewett Douglas E. ; Bereiter Tom ; Vetter Bryan ; Banton Randall G. ; Cutts ; Jr. Richard W. ; Westbrook Donald C. ; Fey ; Jr. Krayn W. ; Posdro John ; Debacker Kenneth C. ; Mehta Nikhil A., Fault-tolerant computer system with online recovery and reintegration of redundant components.
  11. Smith Alan J. (Berkeley CA), Instruction execution accelerator for a pipelined digital machine with virtual memory.
  12. Spear Dan (West Hollywood CA) Mayer Larry (Los Angeles CA), Memory management method.
  13. Larsen Larry D. (Raleigh NC) Nuechterlein David W. (Durham NC) O\Donnell Kim E. (Raleigh NC) Rogers Lee S. (Raleigh NC) Sartorius Thomas A. (Raleigh NC) Schultz Kenneth D. (Cary NC) Linzer Harry I. (, Method and apparatus for controlling operation of a cache memory during an interrupt.
  14. Tarsy Gregory (Scotts Valley CA) Woodard Michael J. (Fremont CA), Method and apparatus for cost-based heuristic instruction scheduling.
  15. Huck Kamla (Portland OR) Glew Andrew F. (Hillsboro OR) Rodgers Scott D. (Hillsboro OR), Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes.
  16. Sandage David A. (Forest Grove OR) Stanley James C. (Portland OR) Hunt Stewart W. (Portland OR) Kunz Arland D. (Beaverton OR), Method and apparatus for sharing a common routine stored in a single virtual machine with other virtual machines operati.
  17. Evoy David Ross ; Levy Paul S., Multiple native instruction set master/slave processor arrangement and method thereof.
  18. Adams Phillip M., Pin management of accelerator for interpretive environments.
  19. Hartung Michael H. (Tucson AZ) Nolta Arthur H. (Tucson AZ) Reed David G. (Tucson AZ), Roll mode for cached data storage.
  20. Alpert Donald B. (Santa Clara CA) Oz Oved (Saba ILX) Intrater Gideon (Ramat-Gan ILX) Marko Reuven (Natanya ILX) Shacham Alon (Tel-Aviv ILX), Selectively locking memory locations within a microprocessor\s on-chip cache.
  21. Blomgren James S. (San Jose CA) Richter David E. (San Jose CA), Shared register architecture for a dual-instruction-set CPU.
  22. Stimac Gary A. (Houston TX) Crosswy William C. (Houston TX) Preston Stephen B. (Spring TX) Flannigan James S. (Cypress TX), Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management.
  23. Gregor Steven L. (Endicott NY), Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage.
  24. Collins Robert W. (2404 NW. 4 Ave. Rochester MN 55901) Hoffman Roy L. (Rte. #2 Pine Island MN 55963) Loen Larry W. (2203 NW. 17 Ave. Rochester MN 55901) Mitchell Glen R. (Rte. #1 Pine Island MN 55963, Synchronizing mechanism for page replacement control.
  25. Denton James L. (Rochester MN) Eickemeyer Richard James (Rochester MN) Griffin Kevin Curtis (Rochester MN) Johnson Ross Evan (Rochester MN) Kunkel Steven Raymond (Rochester MN) Lipasti Mikko Herman (, System and method for increasing cache efficiency through optimized data allocation.
  26. Gregor Steven L. (Endicott NY) Iannucci Robert A. (Andover MA), System for synchronizing execution by a processing element of threads within a process using a state indicator.
  27. Kardach James (San Jose CA) Nguyen Cau (Milpitas CA), Transparent system interrupts with integrated extended memory addressing.
  28. Taylor George S. (Menlo Park CA) Farmwald Michael P. (Berkeley CA), Two-level translation look-aside buffer using partial addresses for enhanced speed.
  29. Raman Srinivas (Folsom CA), Write back cache coherency module for systems with a write through cache supporting bus.
  30. Young Mark, Write through virtual cache memory, alias addressing, and cache flushes.

이 특허를 인용한 특허 (8)

  1. Kobayashi,Tetsuyuki, Intermediate code preprocessing apparatus, intermediate code execution apparatus, intermediate code execution system, and computer program product for preprocessing or executing intermediate code.
  2. Schelling, Todd A.; Meyers, Jr., Ronald P., Memory hole modification and mixed technique arrangements for maximizing cacheable memory space.
  3. Branch, Robert A.; Nachimuthu, Murugasamy K.; Muthusamy, Sundar, Memory mapping.
  4. Yang, Hong Kui; Su, Jing, Method and apparatus for adaptive multi-stage multi-threshold detection of paging indicators in wireless communication systems.
  5. Damodaran, Raguram; Chachad, Abhijeet Ashok; Bhoria, Naveen, Programmable address-based write-through cache control.
  6. Peterson, Robert R., Runtime machine analysis of applications to select methods suitable for method level caching.
  7. Peterson, Robert R., Runtime machine supported method level caching.
  8. Strongin, Geoffrey S.; Barnes, Brian C.; Schmidt, Rodney, System and method providing region-granular, hardware-controlled memory encryption.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로