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Method and apparatus for depositing and controlling the texture of a thin film 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C25D-005/52
  • C25D-005/50
  • C25D-005/00
출원번호 US-0373681 (1999-08-13)
발명자 / 주소
  • Cyprian Emeka Uzoh
  • Homayoun Talieh
출원인 / 주소
  • Nutool, Inc.
대리인 / 주소
    Pillsbury Winthrop LLP
인용정보 피인용 횟수 : 71  인용 특허 : 17

초록

The present invention provides a method and apparatus for plating a conductive material to a substrate and also modifying the physical properties of a conductive film while the substrate is being plated. The present invention further provides a method and apparatus that plates a conductive material

대표청구항

1. A method for altering the texture of a top portion of a conductive layer formed on a substrate, the method comprising the steps of:(1) plating the conductive layer on the substrate by applying a plating solution thereto using an anode and a pad disposed in proximity to the substrate, when the ano

이 특허에 인용된 특허 (17)

  1. Talieh Homayoun (San Jose CA), Chemical mechanical polishing apparatus with improved slurry distribution.
  2. Brusic Vlasta A. ; Marino Jeffrey Robert ; O'Sullivan Eugene John ; Sambucetti Carlos Juan ; Schrott Alejandro Gabriel ; Uzoh Cyprian Emeka, Cobalt-tin alloys and their applications for devices, chip interconnections and packaging.
  3. Uzoh Cyprian E., Continuous highly conductive metal wiring structures and method for fabricating the same.
  4. Palnik Karl (Huntingdon Valley PA), Electrolytic plating apparatus.
  5. Dubin Valery, Electroplating apparatus.
  6. Ichinose Hirofumi,JPX ; Sawayama Ippei,JPX ; Hasebe Akio,JPX ; Murakami Tsutomu,JPX ; Hisamatsu Masaya,JPX ; Shinkura Satoshi,JPX ; Ueno Yukie,JPX, Etching method and process for producing a semiconductor element using said etching method.
  7. Talieh Homayoun (Santa Clara County CA) Weldon David Edwin (Santa Cruz County CA), Linear polisher and method for semiconductor wafer planarization.
  8. Talieh Homoyoun (Sunnyvale CA) Tepman Avi (Cupertino CA) Kieu Hoa Thi (Sunnyvale CA) Wang Chien-Rhone (Milpitas CA), Material deposition method for integrated circuit manufacturing.
  9. Talieh Homayoun, Method and apparatus for electro-chemical mechanical deposition.
  10. Kadija Igor V. (118 Sherwood Rd. Ridgewood NJ 07450), Method and apparatus for manufacturing interconnects with fine lines and spacing.
  11. Kosaki Katsuya (Itami JPX), Method for manufacturing semiconductor device contact.
  12. Uzoh Cyprian Emeka ; Harper James McKell Edwin, Method of electrochemical mechanical planarization.
  13. Liu Yauh-Ching ; Perng Dung-Ching, Method of single step damascene process for deposition and global planarization.
  14. Simon Andrew H. ; Uzoh Cyprian E., Open-bottomed via liner structure and method for fabricating same.
  15. Ishida Hirofumi (Kanagawa JPX), Plating device for wafer.
  16. Watts John D. (2 Mohawk Drive Clinton CT 06413), Surface finishing and plating method.
  17. Talieh Homayoun (San Jose CA) Weldon David E. (Los Gatos CA) Nagorski Boguslaw A. (San Jose CA), Wafer polishing machine with fluid bearings.

이 특허를 인용한 특허 (71)

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