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Method to build multi level structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0382110 (1999-08-24)
발명자 / 주소
  • Cyprian E. Uzoh
  • Daniel C. Edelstein
  • Cheryl Faltermeier
  • Peter S. Locke
출원인 / 주소
  • International Business Machines Corp.
대리인 / 주소
    Connolly Bove Lodge & Hutz, LLP
인용정보 피인용 횟수 : 21  인용 특허 : 22

초록 ▼

A method for forming a structure. A first dielectric material is deposited on a substrate. The first dielectric material is patterned. At least one metal is deposited in and on the first dielectric material. Portions of the at least one metal are removed at least in a region above an upper surface o

대표청구항 ▼

1. A method for forming a structure, the method comprising:a) depositing a first dielectric material on a substrate; b) patterning the first dielectric material; c) depositing at least one metal in openings in the patterned first dielectric and on the patterned first dielectric material; d) removing

이 특허에 인용된 특허 (22)

  1. Brusic Vlasta A. ; Marino Jeffrey Robert ; O'Sullivan Eugene John ; Sambucetti Carlos Juan ; Schrott Alejandro Gabriel ; Uzoh Cyprian Emeka, Cobalt-tin alloys and their applications for devices, chip interconnections and packaging.
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  2. Burghartz Joachim Norbert ; Edelstein Daniel Charles ; Jahnes Christopher Vincent ; Uzoh Cyprian Emeka, Integrated circuit toroidal inductor.
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  3. Wagganer Eric D., Lithographic method for creating damascene metallization layers.
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  4. Ho Yu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Emesh Ismail T. (Cumberland CAX), Method for forming interconnect structures for integrated circuits.
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  5. Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX) Smith Douglas M. (Albuquerque NM), Method for forming porous composites as a low dielectric constant layer with varying porosity distribution electronics a.
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  6. Uzoh Cyprian Emeka ; Harper James McKell Edwin, Method of electrochemical mechanical planarization.
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  7. Potter Curtis N. (Austin TX) Smith Lawrence N. (Austin TX) Kroger Harry (Austin TX), Method of fabricating a high density electrical interconnect.
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  8. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), Method of fabricating a high performance interconnect system for an integrated circuit.
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  9. Huang Chen-Nan,TWX ; Lu Horng-Bor,TWX, Method of fabricating a shallow-trench isolation structure in an integrated circuit.
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  10. Ahn Kie Y., Method of fabricating integrated circuit wiring with low RC time delay.
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  11. Kaja Suryanarayana (Hopewell Junction NY) O\Sullivan Eugene J. (Nyack NY) Schrott Alejandro G. (New York NY), Multilayer interconnect systems.
    상세보기
  12. Jeng Shin-Puu (Plano TX), Porous insulator for line-to-line capacitance reduction.
    상세보기
  13. Anderson, Jr., Herbert R.; Araps, Constance J.; Lotsko, Catherine A., Process for forming metal patterns wherein metal is deposited on a thermally depolymerizable polymer and selectively removed.
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  14. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance.
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  15. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
    상세보기
  16. Numata Ken (Dallas TX) Houston Kay L. (Richardson TX), Reliability of metal leads in high speed LSI semiconductors using dummy vias.
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  17. Jeng Shin-Puu (Plano TX), Selective formation of low-density, low-dielectric-constant insulators in narrow gaps for line-to-line capacitance reduc.
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  18. Kudoh Osamu (Tokyo JPX) Okada Kenji (Tokyo JPX) Shiba Hiroshi (Tokyo JPX) Katoh Takuya (Tokyo JPX), Semiconductor device having multi-level wiring.
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  19. Yao Liang-Gi,TWX, Structure and method for fabricating an interlayer insulating film.
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  20. Young Peter L. (South Barrington IL) Cech Jay (Elmhurst IL) Li Kin (Lombard IL), Thin-film electrical connections for integrated circuits.
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  21. Carey David H. (Austin TX) Pietila Douglass A. (Puyallup WA) Sigmond David M. (Austin TX), Trenching techniques for forming channels, vias and components in substrates.
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  22. Anderson ; Jr. Herbert R. (Patterson NY) Sachdev Harbans S. (Wappingers Falls NY) Sachdev Krishna G. (Wappingers Falls NY), Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes.
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이 특허를 인용한 특허 (21)

  1. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
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  2. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
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  3. Stamper, Anthony K.; Cooney, III, Edward C.; Gambino, Jeffrey P.; Dalton, Timothy J.; Fitzsimmons, John A.; Nicholson, Lee M., Damascene interconnect structures including etchback for low-k dielectric materials.
    상세보기
  4. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
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  5. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.
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  6. Farrar, Paul A., Integrated circuit insulators and related methods.
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  7. Farrar, Paul A., Integrated circuit insulators and related methods.
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  8. Torres, Joaquin; Gosset, Laurent Georges, Integration control and reliability enhancement of interconnect air cavities.
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  9. Chen,Shyng Tsong; Chiras,Stefanie Ruth; Colburn,Matthew Earl; Dalton,Timothy Joseph; Hedrick,Jeffrey Curtis; Huang,Elbert Emin; Kumar,Kaushik Arun; Lane,Michael Wayne; Malone,Kelly; Narayan,Chandrase, Line level air gaps.
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  10. Hung, Ching-Wen; Wu, Jia-Rong; Huang, Chih-Sen, Method for fabricating fin-shaped field-effect transistor.
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  11. Daubenspeck, Timothy H.; Landers, William F.; Zupanski-Nielsen, Donna S., Method for fabricating last level copper-to-C4 connection with interfacial cap structure.
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  12. Sung,Shu Jen, Method of fabricating interconnect.
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  13. Adem, Ercan; Sanchez, John E.; Erb, Darrell M.; Pangrle, Suzette K., Method of forming a selective barrier layer using a sacrificial layer.
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  14. Broekaart, Marcel Eduard Irene; Guelen, Josephus Franciscus Antonius Maria; Gerritsen, Eric, Method of forming an etch stop layer in a semiconductor device.
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  15. Rhee,Seung Hyun; Huang,Richard J.; Gabriel,Calvin T., Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set.
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  16. Wong,Lawrence D.; Leu,Jihperng; Kloster,Grant; Ott,Andrew; Morrow,Patrick, Method of making semiconductor device using a novel interconnect cladding layer.
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  17. Han, Licheng; Yi, Xu; Chooi, Simon; Zhou, Mei Sheng; Xie, Joseph Zhifeng, Method of using silicon rich carbide as a barrier material for fluorinated materials.
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  18. Angyal, Matthew S.; Bao, Junjing; Bonilla, Griselda; Choi, Samuel S.; Culp, James A.; Dyer, Thomas W.; Filippi, Ronald G.; Greco, Stephen E.; Lustig, Naftali E.; Simon, Andrew H., Selective local metal cap layer formation for improved electromigration behavior.
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  19. Angyal, Matthew S.; Bao, Junjing; Bonilla, Griselda; Choi, Samuel S.; Culp, James A.; Dyer, Thomas W.; Filippi, Ronald G.; Greco, Stephen E.; Lustig, Naftali E.; Simon, Andrew H., Selective local metal cap layer formation for improved electromigration behavior.
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  20. Filippi, Ronald G.; Kaltalioglu, Erdem; Wang, Ping-Chuan; Zhang, Lijuan, Selective local metal cap layer formation for improved electromigration behavior.
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  21. Filippi, Ronald G.; Kaltalioglu, Erdem; Wang, Ping-Chuan; Zhang, Lijuan, Selective local metal cap layer formation for improved electromigration behavior.
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