초록 ▼

A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is for

A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.

대표청구항 ▼

1. A method of forming a transistor with associated source and drain regions in the fabrication of an integrated circuit device comprising:providing a gate electrode overlying a gate dielectric layer on a substrate wherein a hard mask layer overlies a top surface of said gate dielectric layer; formi

1. A method of forming a transistor with associated source and drain regions in the fabrication of an integrated circuit device comprising:providing a gate electrode overlying a gate dielectric layer on a substrate wherein a hard mask layer overlies a top surface of said gate dielectric layer; forming an oxide layer overlying said substrate and sidewalls of said gate; forming first spacers on sidewalls of said gate electrode and overlying said oxide layer; forming source/drain extensions in said substrate using said first spacers as a mask; forming second spacers on said first spacers; forming source and drain regions in said substrate using said first and second spacers as a mask; depositing a dielectric layer overlying said gate electrode and said oxide layer and planarizing said dielectric layer to said hard mask layer whereby said first spacers and said second spacers are exposed; removing exposed said second spacers whereby said oxide layer underlying said second spacers is exposed; removing exposed said oxide layer whereby said semiconductor substrate underlying said second spacers is exposed; etching into exposed said semiconductor substrate to form a microtrench wherein said microtrench undercuts said gate oxide layer at an edge of said gate electrode; filling said microtrench with an epitaxial oxide layer and planarizing said epitaxial oxide layer to said hard mask layer; and thereafter patterning said dielectric layer to form third spacers on said epitaxial oxide layer to complete formation of said transistor and associated source and drain regions in said fabrication of said integrated circuit device.