초록 ▼

A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventin

A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.

대표청구항 ▼

1. An integrated circuit comprising:a semiconductor substrate and a wide-line interconnect on said substrate, said wide-line interconnect including a plurality of narrow interconnects to minimize electromigration, said plurality of narrow interconnects extending, and separated from each other for a

1. An integrated circuit comprising:a semiconductor substrate and a wide-line interconnect on said substrate, said wide-line interconnect including a plurality of narrow interconnects to minimize electromigration, said plurality of narrow interconnects extending, and separated from each other for a portion of a length that lies between a cathode or electron current source and an anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink of said wide-line interconnect, each narrow interconnect having a width, W, and a height, H, such that each narrow interconnect has an aspect ratio defined as W/H which is less than or equal to unity, and said plurality of narrow interconnects being multiple layers of thin film metallization layers.