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Stacked printed circuit board memory module and method of augmenting memory therein 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/14
출원번호 US-0995936 (2001-11-27)
발명자 / 주소
  • Rick Weber
  • Corey Larsen
  • James Howarth
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Knobbe, Martens, Olson and Bear, LLP
인용정보 피인용 횟수 : 76  인용 특허 : 23

초록

A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the d

대표청구항

1. Method of augmenting memory in a stacked memory module, the method comprising:providing a primary circuit board having a first and second surface adapted for mounting electronic components, wherein at least the first surface of the primary board has at least one primary connector and at least one

이 특허에 인용된 특허 (23)

  1. McAuliffe Scott C. (Charlton MA) Coleman Byron D. (Holliston MA), Bus device with closely spaced double sided daughter board.
  2. Palatov Dennis, Computer housing and expansion card format for consumer electronics devices.
  3. Carson John C. (Corona del Mar CA) Some Raphael R. (Irvine CA), Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack.
  4. Smith Gary W., Foldable electronic assembly module.
  5. Smith Gary W. (12376 Oakwood Rd. San Diego CA 92129) Karabatsos Chris (42 Jumping Brook La. Kingston NY 12401), Foldable electronic assembly module.
  6. Wu Andrew L. (Shrewsbury) Smelser Donald W. (Bolton) Bruce ; II E. William (Lunenburg MA) O\Dea John (Galway IRX), High density memory array packaging.
  7. Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard K. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT), Integrated multichip memory module structure.
  8. Copeland Jeffrey P. ; Crowell Jonathan C., Method and apparatus for interconnection of multiple modules.
  9. Rathmell Claude (Austin TX) Vance Carroll S. (Austin TX) Barnes David W. (Austin TX) Hashemi Seyed H. (Austin TX), Method of making three dimensional integrated circuit interconnect module.
  10. Pecone Victor (Austin TX), Modular host local expansion upgrade.
  11. Prager, Jay M.; Gonzales, Roman Y., Readily expandable input/output construction for programmable controller.
  12. Bechtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Testa James (Mountain View CA) Storm Shawn (Mt. View CA), Single in-line memory module.
  13. Bechtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Testa James (Mountain View CA) Storm Shawn (Mt. View CA), Single in-line memory module.
  14. Bechtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Testa James (Mountain View CA) Storm Shawn (Mt. View CA), Single in-line memory module.
  15. Testa James (Mountain View CA) Bechtolsheim Andreas (Stanford CA) Frank Edward (Portola Valley CA) Storm Shawn (Mt. View CA), Single in-line memory module.
  16. Ludwig David E. (Irvine CA) Saunders Christ H. (Laguna Niguel CA) Some Raphael R. (Williston VT) Stuart John J. (Newport Beach CA), Stack of IC chips in lieu of single IC chip.
  17. Derouiche Nour Eddine, Stacked dual in-line package assembly.
  18. Shaffer James M. (Boise) Mauritz Karl H. (Boise) Atkins Glen (Boise ID), Stacked printed circuit board device.
  19. Weber Rick ; Howarth James ; Larsen Corey, Stacked printed circuit board memory module.
  20. Noschese Rocco J. (Wilton CT), Stacked printed circuit boards connected in series.
  21. Chiu Anthony M. (Richardson TX), Three dimensional multi-chip module with integral heat sink.
  22. Ward Stephen A. (Watertown MA) Pratt Gill A. (Lexington MA) Nguyen John N. (Belmont MA) Pezaris John S. (Winchester MA) Margolus Norman (Somerville MA), Three-dimensional interconnect having modules with vertical top and bottom connectors.
  23. Rebhahn, Robert W. J.; Cook, Wayne L., Ultrafiltration process for purification of dyes useful in foodstuffs.

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  1. Smith, Michael John Sebastian; Rosenband, Daniel L.; Wang, David T.; Rajan, Suresh Natarajan, Adjusting the timing of signals associated with a memory system.
  2. Smith, Michael John; Rosenband, Daniel L.; Wang, David T.; Rajan, Suresh Natarajan, Adjusting the timing of signals associated with a memory system.
  3. Zeng,Guang; Moore,Roger; Dias,Clive, Anchoring member to facilitate fastening daughter boards to a mother board and a method for use.
  4. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Combined signal delay and power saving for use with a plurality of memory circuits.
  5. Wehrly, Jr.,James Douglas, Composite core circuit module system and method.
  6. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Configurable memory circuit system and method.
  7. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Configurable memory circuit system and method.
  8. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastien; Wang, David T.; Weber, Frederick Daniel, Configurable memory circuit system and method.
  9. Rajan, Suresh Natarajan; Wang, David T., Configurable memory system with interface circuit.
  10. Rajan, Suresh Natarajan; Wang, David T., Configurable multirank memory system with interface circuit.
  11. Rajan, Suresh Natarajan; Schakel, Keith R; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Delaying a signal communicated from a system to at least one of a plurality of memory circuits.
  12. Kinsley,Thomas H., Edge connector including internal layer contact, printed circuit board and electronic module incorporating same.
  13. Kinsley,Thomas H., Edge connector including internal layer contact, printed circuit board and electronic module incorporating same.
  14. Tullidge,Lee H.; Tillinghast,William M., Electronics packaging assembly with parallel circuit boards and a vibration stiffener.
  15. Zohni, Wael O.; Schmidt, William L.; Smith, Michael John Sebastian; Plunkett, Jeremy Matthew, Embossed heat spreader.
  16. Zohni, Wael O.; Schmidt, William; Smith, Michael J. S.; Plunkett, Jeremy Matthew, Embossed heat spreader.
  17. Smith, Michael John Sebastian; Rajan, Suresh Natarajan; Wang, David T, Emulation of abstracted DIMMS using abstracted DRAMS.
  18. Smith, Michael J. S.; Rajan, Suresh Natarajan; Wang, David T., Emulation of abstracted DIMMs using abstracted DRAMs.
  19. Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
  20. Rosenband, Daniel L.; Weber, Frederick Daniel; Smith, Michael John Sebastian, Hybrid memory module.
  21. Rajan, Suresh N., Integrated memory core and memory interface circuit.
  22. Rajan,Suresh Natarajan; Schakel,Keith R.; Smith,Michael John Sebastian; Wang,David T.; Weber,Frederick Daniel, Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits.
  23. Rajan,Suresh Natarajan; Schakel,Keith R.; Smith,Michael John Sebastian; Wang,David T.; Weber,Frederick Daniel, Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit.
  24. Rajan,Suresh Natarajan; Schakel,Keith R.; Smith,Michael John Sebastian; Wang,David T.; Weber,Frederick Daniel, Interface circuit system and method for performing power management operations utilizing power management signals.
  25. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Interface circuit system and method for performing power saving operations during a command-related latency.
  26. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation system and method with refresh capabilities.
  27. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit simulation with power saving capabilities.
  28. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
  29. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
  30. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory circuit system and method.
  31. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory device with emulated characteristics.
  32. Huang, Shaowu; Lee, Beom-Taek, Memory module adaptor card.
  33. Huang, Shaowu; Lee, Beom-Taek, Memory module adaptor card.
  34. Huang, Shaowu; Lee, Beom-Taek, Memory module adaptor card.
  35. Lee,Dong Yang, Memory module and memory system.
  36. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilites.
  37. Rajan, Suresh N.; Schakel, Keith R; Smith, Michael J. S.; Wang, David T; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
  38. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael J. S.; Wang, David T.; Weber, Frederick Daniel, Memory module with memory stack and interface with enhanced capabilities.
  39. Muff,Simon; Raghuram,Siva, Memory module, memory extension memory module, memory module system, and method for manufacturing a memory module.
  40. Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory modules with reliability and serviceability functions.
  41. Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory refresh apparatus and method.
  42. Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Memory refresh apparatus and method.
  43. Wang, David T.; Rajan, Suresh Natarajan, Memory system for synchronous data transmission.
  44. Smith, Michael J. S.; Rajan, Suresh Natarajan, Memory systems and memory modules.
  45. Smith, Michael John Sebastian; Rajan, Suresh Natarajan, Memory systems and memory modules.
  46. Rajan, Suresh N.; Smith, Michael J. S.; Wang, David T, Methods and apparatus of stacking DRAMs.
  47. Rajan,Suresh N., Methods and apparatus of stacking DRAMs.
  48. Brundage, Gary L., Modular sensor systems with elastomeric connectors.
  49. Rajan, Suresh Natarajan; Smith, Michael John, Multi-rank partial width memory modules.
  50. Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
  51. Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Multi-rank partial width memory modules.
  52. Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
  53. Wang, Min; Ferolito, Philip Arnold; Rajan, Suresh Natarajan; Smith, Michael John Sebastian, Optimal channel design for memory devices for providing a high-speed memory interface.
  54. Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Performing error detection on DRAMs.
  55. Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Power management of memory circuits by virtual memory simulation.
  56. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Power saving system and method for use with a plurality of memory circuits.
  57. Ferolito, Philip Arnold; Rosenband, Daniel L.; Wang, David T.; Smith, Michael John Sebastian, Programming of DIMM termination resistance values.
  58. Schakel, Keith R.; Rajan, Suresh Natarajan; Smith, Michael John Sebastian; Wang, David T., Refresh management of memory modules.
  59. Brunelle, Steven J.; Momenpour, Saeed, Reversed memory module socket and motherboard incorporating same.
  60. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a different number of memory circuit devices.
  61. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Simulating a memory standard.
  62. Fjelstad, Joseph C., Stackable low-profile lead frame package.
  63. Sandy,Douglas L.; Harris,Jeffrey M.; Tufford,Robert C., Stacked 3U payload module unit.
  64. Wang, David T.; Rajan, Suresh Natarajan, Stacked DIMM memory interface.
  65. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits.
  66. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
  67. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
  68. Danilak, Radoslav; Smith, Michael J. S.; Rajan, Suresh, System and method for increasing capacity, performance, and flexibility of flash storage.
  69. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for power management in memory systems.
  70. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
  71. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for reducing command scheduling constraints of memory circuits.
  72. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
  73. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, System and method for simulating an aspect of a memory circuit.
  74. Rajan, Suresh Natarajan, System including memory stacks.
  75. Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Wang, David T.; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
  76. Wang, David T.; Rajan, Suresh Natarajan; Schakel, Keith R.; Smith, Michael John Sebastian; Weber, Frederick Daniel, Translating an address associated with a command communicated between a system and memory circuits.
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