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Programmable sub-surface aggregating metallization structure and method of making same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-013/00
출원번호 US-0555612 (2000-07-27)
국제출원번호 PCT/US98/25830 (1998-12-04)
§371/§102 date 20000727 (20000727)
국제공개번호 WO99/28914 (1999-06-10)
발명자 / 주소
  • Michael N. Kozicki
  • William C. West
출원인 / 주소
  • Arizona Board of Regents
대리인 / 주소
    Snell & Wilmer LLP
인용정보 피인용 횟수 : 277  인용 특허 : 12

초록

A programmable sub-surface aggregating metallization sructure ("PSAM") includes an ion conductor such as a chalcogenide-glass which includes metal ions and at least two electrodes disposed at opposing surfaces of the ion conductor. Preferably, the ion conductor includes a chalcogenide material with

대표청구항

1. A programmable sub-surface aggregating metallization (PSAM) structure comprising:an ion conductor; a plurality of electrodes disposed on said ion conductor, wherein at least two of said electrodes are configured for growing a metal dendrite from the negative of the two electrodes toward the posit

이 특허에 인용된 특허 (12)

  1. Neale Ronald G. (Indian Harbour Beach FL), Amorphous non-volatile ram.
  2. Sprague David S. (Portola Valley CA) Woo Arthur N. (Cupertino CA), Map reading system for indicating a user\s position on a published map with a global position system receiver and a data.
  3. Loomis Peter Van Wyck (Sunnyvale CA) Farmer Dominic G. (Milpitas CA), Memory cartridge for a handheld electronic video game.
  4. Klersy Patrick ; Pashmakov Boil ; Czubatyj Wolodymyr ; Kostylev Sergey ; Ovshinsky Stanford R., Memory element with energy control mechanism.
  5. Kozicki Michael N. (Phoenix AZ), Personal electronic dosimeter.
  6. Buckley William D. (1035 Kirts Road Troy MI 48084), Process of making a filament-type memory semiconductor device.
  7. Kozicki Michael N. ; West William C., Programmable metallization cell structure and method of making same.
  8. Kozicki Michael N. ; West William C., Programmable metallization cell structure and method of making same.
  9. Ovshinsky Stanford R. (Bloomfield Hills MI), Recording and retrieving information in an amorphous memory material using a catalytic material.
  10. Klersy Patrick J. (Madison Heights MI) Jablonski David C. (Waterford MI) Ovshinsky Stanford R. (Bloomfield Hills MI), Thin-film structure for chalcogenide electrical switching devices and process therefor.
  11. Ovshinsky Stanford R. ; Pashmakov Boil, Universal memory element and method of programming same.
  12. Nakamura Takashi (Kyoto JPX), Variable resistor and neuro device using the variable resistor for weighting.

이 특허를 인용한 특허 (277)

  1. Daley, Jon; Campbell, Kristy A.; Brooks, Joseph F., Access transistor for memory device.
  2. Daley, Jon; Campbell, Kristy A.; Brooks, Joseph F., Access transistor for memory device.
  3. Daley, Jon; Campbell, Kristy A.; Brooks, Joseph F., Access transistor for memory device.
  4. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Addressable and electrically reversible memory switch.
  5. Li, Jiutao, Agglomeration elimination for metal sputter deposition of chalcogenides.
  6. Li, Jiutao, Agglomeration elimination for metal sputter deposition of chalcogenides.
  7. Li, Jiutao, Agglomeration elimination for metal sputter deposition of chalcogenides.
  8. Li, Jiutao, Agglomeration elimination for metal sputter deposition of chalcogenides.
  9. Li, Jiutao, Agglomeration elimination for metal sputter deposition of chalcogenides.
  10. Moore, John, Apparatus and method for dual cell common electrode PCRAM memory device.
  11. Wang, Zhigang; Dhaoui, Fethi; McCollum, John; Bellippady, Vidyadhara, Array and control method for flash based FPGA cell.
  12. Campbell,Kristy A., Assemblies displaying differential negative resistance.
  13. Campbell, Kristy A., Assemblies displaying differential negative resistance, semiconductor constructions, and methods of forming assemblies displaying differential negative resistance.
  14. Greene, Jonathan; Hawley, Frank W.; McCollum, John, Back to back resistive random access memory cells.
  15. Greene, Jonathan; Hawley, Frank; McCollum, John, Back to back resistive random access memory cells.
  16. Moore, John T.; Gilton, Terry L., Chalcogenide comprising device.
  17. Campbell, Kristy A.; Gilton, Terry L.; Moore, John T.; Brooks, Joseph F., Chalcogenide glass constant current device, and its method of fabrication and operation.
  18. Campbell, Kristy A.; Gilton, Terry L.; Moore, John T.; Brooks, Joseph F., Chalcogenide glass constant current device, and its method of fabrication and operation.
  19. Campbell, Kristy A.; Gilton, Terry L.; Moore, John T.; Brooks, Joseph F., Chalcogenide glass constant current device, and its method of fabrication and operation.
  20. Campbell,Kristy A., Chalcogenide-based electrokinetic memory element and method of forming the same.
  21. Kamalanathan, Deepak; Echeverry, Juan Pablo Saenz; Gopinath, Venkatesh P., Circuits and methods for placing programmable impedance memory elements in high impedance states.
  22. Hecht, Volker, Circuits and methods for preventing over-programming of ReRAM-based memory cells.
  23. Li, Jiutao; McTeer, Allen; Herdt, Gregory; Doan, Trung T., Co-sputter deposition of metal-doped chalcogenides.
  24. Li,Jiutao; McTeer,Allen; Herdt,Gregory; Doan,Trung T., Co-sputter deposition of metal-doped chalcogenides.
  25. Li,Jiutao; McTeer,Allen; Herdt,Gregory; Doan,Trung T., Co-sputter deposition of metal-doped chalcogenides.
  26. Nejad,Hasan; Seyyedy,Mirmajid, Columnar 1T-N memory cell structure.
  27. Hush, Glen; Baker, Jake, Complementary bit PCRAM sense amplifier and method of operation.
  28. Hush, Glen; Baker, Jake, Complementary bit PCRAM sense amplifier and method of operation.
  29. Hush,Glen; Baker,Jake, Complementary bit resistance memory sensor and method of operation.
  30. Ma, Yi; Gopalan, Chakravarthy; Gallo, Antonio R.; Wang, Janet, Conducting bridge random access memory (CBRAM) device structures.
  31. Campbell, Kristy A., Continuously variable resistor.
  32. Kozicki, Michael N.; Ren, Minghan, Dendritic metal structures, methods for making dendritic metal structures, and devices including them.
  33. Kozicki, Michael N., Dendritic structures and tags.
  34. Kozicki, Michael N., Dendritic structures and tags.
  35. Kozicki, Michael N., Dendritic structures and tags.
  36. Kozicki, Michael N., Dendritic structures and tags.
  37. Mei, Ping; Jackson, Warren, Device having a state dependent upon the state of particles dispersed in a carrier.
  38. Campbell, Kristy A., Differential negative resistance memory.
  39. Campbell,Kristy A., Differential negative resistance memory.
  40. Campbell,Kristy A., Differential negative resistance memory.
  41. Hush, Glen; Duesman, Kevin G.; Casper, Steve, Dual write cycle programmable conductor memory system and method of operation.
  42. Sakamoto, Toshitsugu; Aono, Masakazu; Hasegawa, Tsuyoshi; Nakayama, Tomonobu; Terabe, Kazuya; Kawaura, Hisao; Sugibayashi, Tadahiko, Electric device using solid electrolyte.
  43. Kozicki, Michael, Electrical devices including dendritic metal electrodes.
  44. Bulovic,Vladimir; Mandell,Aaron; Perlman,Andrew, Electrically addressable memory switch.
  45. Moore,John T.; Brooks,Joseph F., Electrode structure for use in an integrated circuit.
  46. Li, Jiutao; McTeer, Allen, Elimination of dendrite formation during metal/chalcogenide glass deposition.
  47. Li, Jiutao; McTeer, Allen, Elimination of dendrite formation during metal/chalcogenide glass deposition.
  48. Liu, Jun, Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication.
  49. Liu, Jun, Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication.
  50. Campbell,Kristy A.; Moore,John T.; Gilton,Terry L., Fabrication of single polarity programmable resistance structure.
  51. Mandell, Aaron; Perlman, Andrew, Floating gate memory device using composite molecular material.
  52. Li, Jiutao; Hampton, Keith; McTeer, Allen, Forming a memory device using sputtering to deposit silver-selenide film.
  53. Greene, Jonathan; Hawley, Frank W.; McCollum, John, Front to back resistive random access memory cells.
  54. Greene, Jonathan; Hawley, Frank W.; McCollum, John, Front to back resistive random access memory cells.
  55. Greene, Jonathan; Hawley, Frank; McCollum, John, Front to back resistive random access memory cells.
  56. Moore, John T.; Gilton, Terry L.; Campbell, Kristy A., Graded GeSeconcentration in PCRAM.
  57. Moore, John T.; Gilton, Terry L.; Campbell, Kristy A., Graded GexSe100-x concentration in PCRAM.
  58. Li, Jiutao; McTeer, Allen, Integrated circuit device and fabrication using metal-doped chalcogenide materials.
  59. Li, Jiutao; McTeer, Allen, Integrated circuit device and fabrication using metal-doped chalcogenide materials.
  60. Li, Jiutao; McTeer, Allen, Integrated circuit device and fabrication using metal-doped chalcogenide materials.
  61. Liaw,Corvin; Willer,Josef, Integrated memory device and method for operating the same.
  62. Perner,Martin, Integrated semiconductor memory.
  63. Campbell, Kristy A.; Li, Jiutao; McTeer, Allen; Moore, John T., Layered resistance variable memory device and method of fabrication.
  64. Campbell, Kristy A.; Li, Jiutao; McTeer, Allen; Moore, John T., Layered resistance variable memory device and method of fabrication.
  65. Campbell,Kristy A.; Li,Jiutao; McTeer,Allen; Moore,John T., Layered resistance variable memory device and method of fabrication.
  66. McCollum, John L.; Hamdy, Esmat Z., Low leakage ReRAM FPGA configuration cell.
  67. Moore,John T.; Gilton,Terry L., Memory architecture and method of manufacture and operation thereof.
  68. Moore,John T.; Gilton,Terry L., Memory architecture and method of manufacture and operation thereof.
  69. Moore,John T.; Gilton,Terry L., Memory architecture and method of manufacture and operation thereof.
  70. Moore,John T.; Gilton,Terry L., Memory architecture and method of manufacture and operation thereof.
  71. Moore,John T.; Gilton,Terry L., Memory architecture containing a high density memory array of semi-volatile or non-volatile memory elements.
  72. Daley,Jon, Memory array for increased bit density.
  73. Daley, Jon, Memory array for increased bit density and method of forming the same.
  74. Li,Li; Li,Jiutao, Memory cell intermediate structure.
  75. Liu, Jun, Memory cells with rectifying device.
  76. Liu, Jun, Memory cells with rectifying device.
  77. Gopinath, Venkatesh P.; Shields, Jeffrey Allan; Ma, Yi; Gopalan, Chakravarthy; Kwon, Ming; Dinh, John, Memory cells with vertically integrated tunnel access device and programmable impedance element.
  78. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  79. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  80. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  81. Krieger, Juri H.; Yudanoy, Nikolai, Memory device.
  82. Takaura, Norikatsu; Terao, Motoyasu; Matsuoka, Hideyuki; Kurotsuchi, Kenzo, Memory device.
  83. Moore, John T.; Campbell, Kristy A., Memory device and methods of controlling resistance variation and resistance profile drift.
  84. R철hr,Thomas, Memory device having an array of resistive memory cells.
  85. Campbell, Kristy A., Memory device incorporating a resistance variable chalcogenide element.
  86. Krieger, Juri H.; Yudanov, N. F., Memory device with a self-assembled polymer film and method of making the same.
  87. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active and passive layers.
  88. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active passive layers.
  89. Campbell,Kristy A., Memory device with switching glass layer.
  90. Moore,John T.; Gilton,Terry L., Memory device, programmable resistance memory cell and memory array.
  91. Moore,John T.; Campbell,Kristy A.; Gilton,Terry L., Memory element and its method of formation.
  92. Yasuda, Shuichiro; Tsushima, Tomohito; Sasaki, Satoshi; Aratani, Katsuhisa, Memory element and memory device.
  93. Yasuda, Shuichiro; Tsushima, Tomohito; Sasaki, Satoshi; Aratani, Katsuhisa, Memory element and memory device.
  94. Aratani, Katsuhisa; Tsushima, Tomohito; Kouchiyama, Akira, Memory element and memory device comprising memory layer positioned between first and second electrodes.
  95. Aratani, Katsuhisa; Tsushima, Tomohito; Kouchiyama, Akira; Mizuguchi, Tetsuya, Memory element and memory device comprising memory layer positioned between first and second electrodes.
  96. Daley, Jon; Brooks, Joseph F., Memory elements having patterned electrodes and method of forming the same.
  97. Daley, Jon; Brooks, Joseph F., Memory elements having patterned electrodes and method of forming the same.
  98. Daley,Jon, Method and apparatus for accessing a memory array.
  99. Ivanov, Milena; Hoenigschmid, Heinz; Dietrich, Stefan, Method and apparatus for an integrated circuit with programmable memory cells, data system.
  100. Campbell,Kristy A., Method and apparatus for providing color changing thin film material.
  101. Campbell,Kristy A., Method and apparatus for resistance variable material cells.
  102. Casper, Stephen L.; Duesman, Kevin; Hush, Glen, Method and apparatus for sensing resistive memory state.
  103. Hush, Glen, Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance.
  104. Hush, Glen, Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance.
  105. Hush, Glen, Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance.
  106. Hush, Glen, Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance.
  107. Hush,Glen, Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance.
  108. Li,Li; Li,Jiutao, Method for filling via with metal.
  109. Gilton, Terry L.; Moore, John T., Method for programming a memory cell.
  110. Moore,John T.; Brooks,Joseph F., Method of fabricating an electrode structure for use in an integrated circuit.
  111. Raberg, Wolfgang; Ufert, Klaus-Dieter, Method of fabricating an integrated electronic circuit with programmable resistance cells.
  112. Moore, John, Method of fabricating dual PCRAM cells sharing a common electrode.
  113. Campbell,Kristy A., Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element.
  114. Moore, John T.; Gilton, Terry L., Method of forming a chalcogenide comprising device.
  115. Brooks,Joseph F., Method of forming a chalcogenide material containing device.
  116. Brooks,Joseph F., Method of forming a chalcogenide material containing device.
  117. Campbell,Kristy A.; Gilton,Terry L.; Moore,John T., Method of forming a memory cell.
  118. Campbell, Kristy A., Method of forming a memory device incorporating a resistance variable chalcogenide element.
  119. Campbell, Kristy A., Method of forming a memory device incorporating a resistance variable chalcogenide element.
  120. Campbell, Kristy A., Method of forming a memory device incorporating a resistance-variable chalcogenide element.
  121. Moore, John T.; Gilton, Terry L., Method of forming a non-volatile resistance variable device.
  122. Campbell,Kristy A.; Moore,John T., Method of forming a programmable memory cell and chalcogenide structure.
  123. Moore,John T.; Campbell,Kristy A.; Gilton,Terry L., Method of forming a resistance variable memory element.
  124. Campbell, Kristy A., Method of forming a variable resistance memory device comprising tin selenide.
  125. Gilton, Terry L., Method of forming and storing data in a multiple state memory cell.
  126. Campbell, Kristy A.; Gilton, Terry L.; Moore, John T.; Li, Jiutao, Method of forming chalcogenide comprising devices.
  127. Campbell, Kristy A.; Moore, John T., Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry.
  128. Campbell, Kristy A.; Moore, John T., Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device.
  129. Moore, John T., Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices.
  130. Moore,John T.; Brooks,Joseph F., Method of forming electrode structure for use in an integrated circuit.
  131. Moore, John T., Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry.
  132. Campbell,Kristy A.; Moore,John T., Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of memory circuitry.
  133. Harshfield,Steven T.; Wright,David Q., Method of making a memory cell.
  134. Moore, John T.; Campbell, Kristy A.; Gilton, Terry L., Method of manufacture of a PCRAM memory cell.
  135. Moore,John T.; Campbell,Kristy A.; Gilton,Terry L., Method of manufacture of a PCRAM memory cell.
  136. Moore,John T.; Campbell,Kristy A.; Gilton,Terry L., Method of manufacture of a resistance variable memory cell.
  137. Gilton,Terry L., Method of manufacture of programmable conductor memory.
  138. Gilton, Terry L., Method of manufacture of programmable switching circuits and memory cells employing a glass layer.
  139. Hush,Glen; Baker,Jake, Method of operating a complementary bit resistance memory sensor.
  140. Hush,Glen; Baker,Jake, Method of operating a complementary bit resistance memory sensor and method of operation.
  141. Moore, John T.; Gilton, Terry L.; Campbell, Kristy A., Method of refreshing a PCRAM memory device.
  142. Moore,John T.; Gilton,Terry L.; Campbell,Kristy A., Method of refreshing a PCRAM memory device.
  143. Gilton, Terry L.; Campbell, Kristy A., Method of retaining memory state in a programmable conductor RAM.
  144. Gilton, Terry L.; Campbell, Kristy A., Method of retaining memory state in a programmable conductor RAM.
  145. Campbell, Kristy A.; Moore, John; Gilton, Terry L.; Brooks, Joseph F., Method to alter chalcogenide glass for improved switching characteristics.
  146. Moore, John T.; Campbell, Kristy A.; Gilton, Terry L., Method to control silver concentration in a resistance variable memory element.
  147. Moore, John T.; Gilton, Terry L., Method to manufacture a buried electrode PCRAM cell.
  148. Campbell, Kristy A., Methods and apparatus for resistance variable material cells.
  149. Moore, John T.; Gilton, Terry L.; Campbell, Kristy A., Methods for forming chalcogenide glass-based memory elements.
  150. Moore,John T.; Gilton,Terry L., Methods of forming a semiconductor memory device.
  151. Li,Li; Li,Jiutao, Methods of forming and using memory cell structures.
  152. Campbell,Kristy A., Methods of forming assemblies displaying differential negative resistance.
  153. Daley, Jon, Methods of forming memory arrays for increased bit density.
  154. Giltom, Terry L.; Campbell, Kristy A.; Moore, John T., Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures.
  155. Naveh, Ishai, Methods of making memory devices with programmable impedance elements and vertically formed access devices.
  156. Moore, John T.; Gilton, Terry L., Methods of metal doping a chalcogenide material.
  157. Campbell,Kristy A.; Gilton,Terry L.; Moore,John T.; Brooks,Joseph F., Methods of operating and forming chalcogenide glass constant current devices.
  158. Moore, John T.; Gilton, Terry L.; Campbell, Kristy A., Methods to form a memory cell with metal-rich metal chalcogenide.
  159. Moore,John T.; Gilton,Terry L.; Campbell,Kristy A., Methods to form a memory cell with metal-rich metal chalcogenide.
  160. Kozicki, Michael N, Microelectric programmable device and methods of forming and programming the same.
  161. Kozicki, Michael N., Microelectronic programmable device and methods of forming and programming the same.
  162. Kozicki, Michael N.; Mitkova, Maria, Microelectronic programmable device and methods of forming and programming the same.
  163. Kozicki,Michael N.; Mitkova,Maria, Microelectronic programmable device and methods of forming and programming the same.
  164. Kozicki,Michael N; Mitkova,Maria, Microelectronic programmable device and methods of forming and programming the same.
  165. Krieger, Juri H.; Yudanov, Nikolay F., Molecular memory cell.
  166. Krieger,Juri H; Yudanov,Nicolay F, Molecular memory cell.
  167. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Molecular memory device.
  168. Philipp, Jan Boris; Happ, Thomas, Multi-level resistive memory cell using different crystallization speeds.
  169. Sunkavalli, Ravi, Multi-port memory devices and methods having programmable impedance elements.
  170. Gilton, Terry L., Multiple data state memory cell.
  171. Gilton,Terry L., Multiple data state memory cell.
  172. Gilton,Terry L., Multiple data state memory cell.
  173. Gilton, Terry L., Non-volatile memory structure.
  174. Gilton, Terry L., Non-volatile memory structure.
  175. Gilton,Terry L., Non-volatile memory structure.
  176. Gilton,Terry L., Non-volatile memory structure.
  177. Moore, John T., Non-volatile resistance variable device.
  178. Campbell,Kristy A.; Moore,John T., Non-volatile resistance variable devices.
  179. Gilton,Terry L., Non-volatile resistance variable devices and method of forming same, analog memory devices and method of forming same, programmable memory cell and method of forming same, and method of structurally .
  180. Jameson, John Ross; Koushan, Foroozan Sarah, Nonvolatile memory elements having conductive structures with semimetals and/or semiconductors.
  181. Kozicki, Michael N., Optimized solid electrolyte for programmable metallization cell devices and structures.
  182. Kingsborough,Richard P.; Sokolik,Igor, Organic thin film Zener diodes.
  183. Campbell, Kristy A., PCRAM device with switching glass layer.
  184. Campbell, Kristy A., PCRAM device with switching glass layer.
  185. Harshfield,Steven T.; Wright,David Q., PCRAM memory cell and method of making same.
  186. Harshfield,Steven T.; Wright,David Q., PCRAM memory cell and method of making same.
  187. Moore, John; Baker, Jake, PCRAM rewrite prevention.
  188. Moore, John; Baker, R. Jacob, PCRAM rewrite prevention.
  189. Campbell, Kristy A., Phase change memory cell and method of formation.
  190. Campbell,Kristy A., Phase change memory cell and method of formation.
  191. Liu, Jun; Violette, Mike, Phase change memory structure with multiple resistance states and methods of programming and sensing same.
  192. Li, Li; Gilton, Terry L.; Ko, Kei-Yu; Moore, John T.; Signorini, Karen, Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes.
  193. Li,Li; Gilton,Terry L.; Ko,Kei Yu; Moore,John T.; Signorini,Karen, Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes.
  194. Hardy, Trevor; Porter, Steve; Williford, Ethan; Ingram, Mark, Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory.
  195. Hardy,Trevor; Porter,Steve; Williford,Ethan; Ingram,Mark, Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory.
  196. Hardy,Trevor; Porter,Steve; Williford,Ethan; Ingram,Mark, Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory.
  197. Klein, Dean A., Power management control and controlling memory refresh operations.
  198. Klein, Dean A., Power management control and controlling memory refresh operations.
  199. Klein, Dean A., Power management control and controlling memory refresh operations.
  200. Daley, Jon, Process for erasing chalcogenide variable resistance memory bits.
  201. Daley,Jon, Process for erasing chalcogenide variable resistance memory bits.
  202. Gilton, Terry L., Programmable conductor memory cell structure and method therefor.
  203. Gilton, Terry L., Programmable conductor memory cell structure and method therefor.
  204. Gilton,Terry L., Programmable conductor memory cell structure and method therefor.
  205. Hush, Glen, Programmable conductor random access memory and a method for writing thereto.
  206. Casper, Stephen L.; Duesman, Kevin; Hush, Glen, Programmable conductor random access memory and method for sensing same.
  207. Gallo, Antonio R.; Koushan, Foroozan Sarah, Programmable impedance memory elements, methods of manufacture, and memory devices containing the same.
  208. Kozicki, Michael N., Programmable metallization cell structure including an integrated diode, device including the structure, and method of forming same.
  209. Kozicki,Michael N.; Balakrishnan,Muralikrishnan, Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same.
  210. Tonti, William R.; Berry, Wayne S.; Fifield, John A.; Guthrie, William H.; Kontra, Richard S., Programmable semiconductor device.
  211. Tonti, William R.; Berry, Wayne S.; Fifield, John A.; Guthrie, William H.; Kontra, Richard S., Programmable semiconductor device.
  212. Tonti, William R.; Berry, Wayne S.; Fifield, John A.; Guthrie, William H.; Kontra, Richard S., Programmable semiconductor device.
  213. Kozicki,Michael N.; Mitkova,Maria; Gopalan,Chakravarthy; Balakrishnan,Muralikrish, Programmable structure including an oxide electrolyte and method of forming programmable structure.
  214. Kozicki,Michael N., Programmable structure, an array including the structure, and methods of forming the same.
  215. Kozicki,Michael N., Programmable surface control devices and method of making same.
  216. Perner,Frederick A., Programming of programmable resistive memory devices.
  217. McCollum, John, Push-pull programmable logic device cell.
  218. Gilton, Terry L.; Doan, Trung T., Removable programmable conductor memory card and associated read/write device and method of operation.
  219. Toda, Haruki; Kubo, Koichi, Resistance change memory device.
  220. Toda,Haruki; Kubo,Koichi, Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation.
  221. Toda,Haruki; Kubo,Koichi, Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode.
  222. Toda, Haruki; Kubo, Koichi, Resistance change memory device with a variable resistance element formed of a first and a second composite compound.
  223. Chang, Ting-Chang; Yang, Po-Chun; Lin, Yu-Shih; Chen, Shih-Ching; Jian, Fu-Yen, Resistance random access memory element and method for making the same.
  224. Gilton, Terry L., Resistance variable device.
  225. Moore,John T., Resistance variable device.
  226. Gilton, Terry L., Resistance variable device, analog memory device, and programmable memory cell.
  227. Harshfield, Steven T.; Wright, David Q., Resistance variable memory cells.
  228. Campbell,Kristy A., Resistance variable memory device and method of fabrication.
  229. Campbell,Kristy A., Resistance variable memory device and method of fabrication.
  230. Campbell,Kristy A., Resistance variable memory device and method of fabrication.
  231. Campbell, Kristy A.; Daley, Jon; Brooks, Joseph F., Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication.
  232. Campbell,Kristy A.; Daley,Jon; Brooks,Joseph F., Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication.
  233. Campbell,Kristy A.; Daley,Jon; Brooks,Joseph F., Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication.
  234. Campbell, Kristy A.; Gilton, Terry L.; Moore, John T.; Li, Jiutao, Resistance variable memory devices with passivating material.
  235. Moore, John T.; Campbell, Kristy A.; Gilton, Terry L., Resistance variable memory element and its method of formation.
  236. Campbell,Kristy A.; Daley,Jon; Brooks,Joseph F., Resistance variable memory element with threshold device and method of forming the same.
  237. Campbell,Kristy A.; Daley,Jon; Brooks,Joseph F., Resistance variable memory element with threshold device and method of forming the same.
  238. Campbell,Kristy A., Resistance variable memory elements and methods of formation.
  239. Campbell, Kristy A., Resistance variable memory with temperature tolerant materials.
  240. Campbell, Kristy A., Resistance variable memory with temperature tolerant materials.
  241. Campbell,Kristy A., Resistance variable memory with temperature tolerant materials.
  242. Campbell,Kristy A., Resistance variable memory with temperature tolerant materials.
  243. Campbell, Kristy A.; Moore, John T.; Gilton, Terry L., Resistance variable ‘on ’ memory.
  244. Greene, Jonathan; Hawley, Frank W.; McCollum, John, Resistive RAM devices for programmable logic devices.
  245. Greene, Jonathan; Hawley, Frank; McCollum, John L., Resistive random access memory cells.
  246. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Reversible field-programmable electric interconnects.
  247. Bulovic,Vladimir; Mandell,Aaron; Perlman,Andrew, Reversible field-programmable electric interconnects.
  248. Moore,John; Baker,R. Jacob, Rewrite prevention in a variable resistance memory.
  249. Yang, Chih-Chao; Cohen, Stephen A; Li, Baozhen, Semiconductor switching device and method of making the same.
  250. Williford,Ethan; Ingram,Mark, Sensing of resistance variable memory devices.
  251. Williford,Ethan; Ingram,Mark, Sensing of resistance variable memory devices.
  252. Li,Jiutao; Hampton,Keith; McTeer,Allen, Silver selenide film stoichiometry and morphology control in sputter deposition.
  253. Li,Jiutao; Hampton,Keith; McTeer,Allen, Silver selenide film stoichiometry and morphology control in sputter deposition.
  254. Campbell, Kristy A.; Moore, John T., Silver-selenide/chalcogenide glass stack for resistance variable memory.
  255. Campbell,Kristy A.; Moore,John T., Silver-selenide/chalcogenide glass stack for resistance variable memory.
  256. Campbell, Kristy A.; Moore, John T., Silver-selenide/chalcogenide glass stack for resistance variable memory and manufacturing method thereof.
  257. Campbell, Kristy A.; Moore, John T.; Gilton, Terry L., Single-polarity programmable resistance-variable memory element.
  258. Liu,Jun; Gilton,Terry L.; Moore,John T., Small electrode for resistance variable devices.
  259. Campbell, Kristy A., SnSe-based limited reprogrammable cell.
  260. Campbell,Kristy A., SnSe-based limited reprogrammable cell.
  261. Gilton, Terry L., Software refreshed memory device and method.
  262. Gilton, Terry L., Software refreshed memory device and method.
  263. Gilton,Terry L., Software refreshed memory device and method.
  264. Gilton,Terry L., Software refreshed memory device and method.
  265. Gopalan, Chakravarthy; Lee, Wei Ti; Ma, Yi; Shields, Jeffrey Allan, Solid electrolyte memory elements with electrode interface for improved performance.
  266. Pinnow, Cay Uwe; Ufert, Klaus Dieter, Solid electrolyte switching element.
  267. Campbell, Kristy A., Stoichiometry for chalcogenide glasses useful for memory devices and method of formation.
  268. Gilton, Terry L., Thin film diode integrated with chalcogenide memory cell.
  269. Gilton,Terry L., Thin film diode integrated with chalcogenide memory cell.
  270. Toda, Haruki, Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array.
  271. Toda, Haruki, Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array.
  272. Toda, Haruki, Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array.
  273. Toda, Haruki, Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array.
  274. Marshall,Joseph R.; Berger,Richard W.; Rodgers,John C., Use of radiation-hardened chalcogenide technology for spaceborne reconfigurable digital processing systems.
  275. Gallo, Antonio R.; Gopalan, Chakravarthy; Ma, Yi, Variable impedance memory device structure and method of manufacture including programmable impedance memory cells and methods of forming the same.
  276. Hush, Glen; Moore, John, Variable resistance memory and method for sensing same.
  277. Ninomiya, Takeki; Mikawa, Takumi; Hayakawa, Yukio, Variable resistance nonvolatile memory element and method for manufacturing the same.
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