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Structure including electronic components singulated using laser cutting 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/304
출원번호 US-0797759 (2001-03-01)
발명자 / 주소
  • Thomas P. Glenn
  • Steven Webster
  • Roy Dale Hollaway
출원인 / 주소
  • Amkor Technology, Inc.
대리인 / 주소
    Gunnison, McKay & Hodgson, L.L.P.
인용정보 피인용 횟수 : 16  인용 특허 : 25

초록

A structure comprises a substrate with electronic components formed on a first surface of the substrate. The structure includes a scribe line on a first surface of the substrate. The structure includes a trench formed by a laser on the second or back-side surface of the substrate, thus protecting th

대표청구항

1. A structure comprising:a substrate, said substrate comprising a substrate first surface and a substrate second surface, opposite said substrate first surface, and a substrate thickness between said substrate first surface and said substrate second surface; a scribe line on said substrate first su

이 특허에 인용된 특허 (25)

  1. Buynoski Mathew S., Control of juction depth and channel length using generated interstitial gradients to oppose dopant diffusion.
  2. Lee Teck Koon,SGX ; Chan Lap ; Gan Chock H.,SGX ; Liu Po-Ching,SGX, Creation of a self-aligned, ion implanted channel region, after source and drain formation.
  3. Hsu Louis L. (Fishkill NY) Mathad Gangadhara S. (Poughkeepsie NY) Joshi Rajiv V. (Yorktown Heights NY), Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps.
  4. Moslehi Mehrdad M., Insulated-gate field-effect transistor structure and method.
  5. Gardner Mark I. ; Hause Fred N. ; Fulford ; Jr. H. Jim, Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance.
  6. Anjum Mohammed (Austin TX) Koop Klaus H. (Elgin TX) Kyaw Maung H. (Austin TX), Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices.
  7. Doyle Brian S. ; Fraser David B., Low temperature method of forming gate electrode and gate dielectric.
  8. Wu Shye-Lin,TWX, MOSFET with self-aligned silicidation and gate-side air-gap structure.
  9. Yeh Wen-Kuan,TWX ; Chen Coming,TWX ; Chou George,TWX, Manufacture of MOSFET having LDD source/drain region.
  10. van Berkum Petrus A. (Elmhurst IL) Mathius Ronald P. (Bridgeview IL), Method for cleaving a semiconductor crystal body.
  11. Kim Young K. (Kyungki KRX) Kim Kyung S. (Seoul KRX) Park Min H. (Seoul KRX), Method for fabricating MOS transistor.
  12. Byun Jeong S. (Chungcheongbuk-do KRX), Method for fabricating MOS transistor having source/drain region of shallow junction and silicide film.
  13. Shell Yau-Kae (Hsinchu TWX) Hong Gary (Hsinchu TWX), Method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel.
  14. Mitani Tatsuro (Tokyo JPX) Fukuda Toshikazu (Kawasaki JPX), Method for manufacturing semiconductor device.
  15. Roberts ; Jr. Carl M. (Topsfield MA) Long Lewis H. (Woburn MA) Ruggerio Paul A. (Campbell CA), Method for separating circuit dies from a wafer.
  16. Bean Kenneth E. (Celina) Powell John (Canton) Freeman Jack W. (Plano TX) McGrath Robert D. (Andover MA), Method of fabricating an integrated circuit having active regions near a die edge.
  17. Kwok Siang P. (Colorado Springs CO), Method of making a self-aligned MESFET using a substitutional gate with side walls.
  18. Kinoshita Junichi,JPX, Method of manufacturing a semiconductor laser including two sets of dicing grooves.
  19. Watanabe Yuu (Hadano JPX), Method of producing semiconductor device using dummy gate structure.
  20. Yoo Chue-San (Taipei TWX) Lin Ting-Hwang (Hsin-Chu TWX), Peeling free metal silicide films using rapid thermal anneal.
  21. Miyasaka Mitsutoshi,JPX ; Little Thomas W.,JPX, Process for fabricating a thin film transistor.
  22. Luftman Henry S. (Emmaus PA) Watts Roderick K. (Summit NJ), Process for fabricating integrated circuit containing shallow junction using dopant source containing organic polymer or.
  23. Ormond Brian T. (Webster NY) Quinn Kraig A. (Webster NY) Hosier Paul A. (Rochester NY) Jedlicka Josef E. (Rochester NY), Process for separating image sensor dies and the like from a wafer that minimizes silicon waste.
  24. Naguib Hussein M. (Fremont CA) Calder Iain D. (Nepean CAX) Ho Vu Q. (Kanata CAX) Naem Abdalla A. (Ottawa CAX), Process of fabricating MOS devices having shallow source and drain junctions.
  25. Orcutt John W., Trench scribe line for decreased chip spacing.

이 특허를 인용한 특허 (16)

  1. Vollertsen, Rolf-Peter, Apparatus and method for measuring local surface temperature of semiconductor device.
  2. Vollertsen, Rolf-Peter, Apparatus and method for measuring local surface temperature of semiconductor device.
  3. Glenn, Thomas P.; Hollaway, Roy Dale; Webster, Steven, Back-side wafer singulation method.
  4. Schrems, Martin; Stering, Bernhard; Schrank, Franz, Dicing method.
  5. Hamaguchi, Norihito; Hasnain, Ghulam, Method and apparatus for manufacturing LED devices using laser scribing.
  6. Brintzinger,Axel; Trovarelli,Octavio, Method for improving the mechanical properties of BOC module arrangements.
  7. Göltl, Claudia; Kuhn, Frank, Method for subdividing wafers into chips.
  8. Shizuno, Yoshinori, Method of dicing a semiconductor device into plural chips.
  9. Swenson, Edward J.; Sun, Yunlong; Sammi, Manoj Kumar; Johnson, Jay Christopher, Method of forming a scribe line on a ceramic substrate.
  10. Swenson,Edward J.; Sun,Yunlong; Sammi,Manoj Kumar; Johnson,Jay Christopher; Garcia,Doug; Anklekar,Rupendra M., Method of forming a scribe line on a passive electronic component substrate.
  11. Huemoeller, Ronald P.; Sheridan, Richard P., Method of making a chip carrier package using laser ablation.
  12. Hurtado,Alejandro, Mounting and dicing process for wafers.
  13. McKerreghan, Michael H.; Islam, Shafidul; San Antonio, Romarico S., Package having exposed integrated circuit device.
  14. Huang,Tai Chun; Chi,Kuan Shou; Yao,Chih Hsiang, Semiconductor chip singulation method.
  15. Kumakawa, Takahiro, Semiconductor substrate, and semiconductor device and method of manufacturing the semiconductor device.
  16. Glenn, Thomas P.; Hollaway, Roy Dale; Webster, Steven, Wafer having alignment marks extending from a first to a second surface of the wafer.
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