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특허 상세정보

Method for instruction extensions for a tightly coupled speculative request unit

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-012/08   
미국특허분류(USC) 711/137; 711/100; 711/122
출원번호 US-0345642 (1999-06-30)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Casimer K. Salys
인용정보 피인용 횟수 : 0  인용 특허 : 30
초록

A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being awa...

대표
청구항

1. A method of operating a processing unit of a computer system, comprising:loading a plurality of program instructions into an instruction sequence unit of the processing unit; determining that at least one of the loaded instructions includes an explicit prefetch indication; issuing the instruction having the explicit prefetch indication directly from the instruction sequence unit to a prefetch unit of the processing unit; and sending a prefetch request from the prefetch unit to prefetch a value residing in a memory hierarchy of the computer system that...

이 특허에 인용된 특허 (30)

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  18. Dubey Pradeep Kumar. Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative condit. USP1998065774685.
  19. Mulchandani Deepak (Austin TX) Gray Rand (Austin TX). Method and apparatus for restoring a target MCU debug session to a prior state. USP1997125701488.
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  27. Mayfield Michael John. System and method for diallocating stream from a stream buffer. USP1998045737565.
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  29. Weisser Pirmin L. (Unterkirnach DEX) Vermeer Fulps V. (Delft CA NLX) King Edward C. (Fremont CA). System and method for prefetching data from a main computer memory into a cache memory. USP1996065530941.
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