[특허]Method for instruction extensions for a tightly coupled speculative request unit

Method for instruction extensions for a tightly coupled speculative request unit 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-012/08
출원번호	US-0345642 (1999-06-30)
발명자 / 주소	Ravi Kumar Arimilli Lakshminarayana Baba Arimilli Leo James Clark John Steven Dodson Guy Lynn Guthrie James Stephen Fields, Jr.
출원인 / 주소	International Business Machines Corporation
대리인 / 주소	Casimer K. Salys
인용정보	피인용 횟수 : 0 인용 특허 : 30

초록 ▼

A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value. The prefetch limit of cache usage may be established with a maximum number of sets in a congruence class usable by the requesting processing unit. A flag in a directory of the cache may be set to indicate that the prefetch value was retrieved as the result of a prefetch operation. In the implementation wherein the cache is a multi-level cache, a second flag in the cache directory may be set to indicate that the prefetch value has been sourced to an upstream cache. A cache line containing prefetch data can be automatically invalidated after a preset amount of time has passed since the prefetch value was requested.

대표청구항 ▼

1. A method of operating a processing unit of a computer system, comprising:loading a plurality of program instructions into an instruction sequence unit of the processing unit; determining that at least one of the loaded instructions includes an explicit prefetch indication; issuing the instruction having the explicit prefetch indication directly from the instruction sequence unit to a prefetch unit of the processing unit; and sending a prefetch request from the prefetch unit to prefetch a value residing in a memory hierarchy of the computer system that is specified in the instruction having the explicit prefetch indication.

이 특허에 인용된 특허 (30)

Jouppi Norman P., Adaptive stream buffers.
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Manasse Mark S. (San Mateo County CA), Competitive snoopy caching for large-scale multiprocessors.
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Mowry Todd C.,CAX, Consistently specifying way destinations through prefetching hints.
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Sokolov Daniel John ; Swatosh Timothy, Disk drive with cache controlled adaptively for amount of prefetch.
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Sokolov Daniel John ; Williams Jeffrey L., Disk drive with cache repeatedly accessed for a read command to provide prefetched data.
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Santhanam Vatsa (Campbell CA), Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instruc.
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Kayser Lyle D. ; Brown T. Gordon, Fold-out fin.
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Ji Brian ; Kirihata Toshiaki ; Mueller Gerhard ; Hanson David, Hierarchical prefetch for semiconductor memories.
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Larson Kenneth N. (Thousand Oaks CA) Davis John S. (Glendale CA) Bostick Lewis M. (Honolulu HI), Information exchange processor.
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Matsubara Kenji,JPX ; Kurihara Toshihiko,JPX ; Imori Hiromitsu,JPX, Information processing unit and method for controlling a hierarchical cache utilizing indicator bits to control content of prefetching operations.
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Yeh Tse-Yu ; Poplingher Mircea ; Fielden Kent G. ; Mulder Hans ; Gupta Rajiv ; Morris Dale ; Schlansker Michael, Instruction prefetch mechanism utilizing a branch predict instruction.
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Westberg Thomas E. (Sudbury MA), Intelligent cache memory and prefetch method based on CPU data fetching characteristics.
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Ramakrishnan Kadangode K. (Maynard MA) Biswas Prabuddha (Nashua NH), Managing the fetching and replacement of cache entries associated with a file system.
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Dubey Pradeep Kumar, Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative condit.
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Mulchandani Deepak (Austin TX) Gray Rand (Austin TX), Method and apparatus for restoring a target MCU debug session to a prior state.
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Tung Victor Wai Ner ; Sne Gal ; Scaringella Stephen Lawrence, Method and apparatus including a shared resource and multiple processors running a common control program accessing the.
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Blomgren James S., Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield.
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Hoffman Roy L. (Pine Island MN) Houdek Merle E. (Rochester MN) Loen Larry W. (Rochester MN) Soltis Frank G. (Rochester MN), Multi-processor task dispatching apparatus.
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Sites Richard Lee ; Witek Richard T., Prefetch instruction for improving performance in reduced instruction set processor.
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Vigil Peter J. ; Lederer Louis S. ; Blomgren James S., Self-testing multi-processor die with internal compare points.
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Dean Mark E. (Austin TX), Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals.
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Carter John B. ; Davis Scott H. ; Dietterich Daniel J. ; Frank Steven J. ; Lee Hsin H., Shared client-side web caching using globally addressable memory.
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Mayfield Michael John, System and method for diallocating stream from a stream buffer.
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Weisser Pirmin L.,DEX ; Vermeer Fulps V.,NLX ; King Edward C., System and method for enhancing computer operation by prefetching data elements on a common bus without delaying bus ac.
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Weisser Pirmin L. (Unterkirnach DEX) Vermeer Fulps V. (Delft CA NLX) King Edward C. (Fremont CA), System and method for prefetching data from a main computer memory into a cache memory.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Method for instruction extensions for a tightly coupled speculative request unit 원문보기

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Method for instruction extensions for a tightly coupled speculative request unit 원문보기

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