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특허 상세정보

Method for instruction extensions for a tightly coupled speculative request unit

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-012/08   
미국특허분류(USC) 711/137; 711/100; 711/122
출원번호 US-0345642 (1999-06-30)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Casimer K. Salys
인용정보 피인용 횟수 : 0  인용 특허 : 30

A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being awa...


1. A method of operating a processing unit of a computer system, comprising:loading a plurality of program instructions into an instruction sequence unit of the processing unit; determining that at least one of the loaded instructions includes an explicit prefetch indication; issuing the instruction having the explicit prefetch indication directly from the instruction sequence unit to a prefetch unit of the processing unit; and sending a prefetch request from the prefetch unit to prefetch a value residing in a memory hierarchy of the computer system that...

이 특허에 인용된 특허 (30)

  1. Jouppi Norman P.. Adaptive stream buffers. USP1999095958040.
  2. Bauman Mitchell (Circle Pines MN) Haupt Michael (Roseville MN). Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed. USP1997025603005.
  3. Manasse Mark S. (San Mateo County CA). Competitive snoopy caching for large-scale multiprocessors. USP1994095345578.
  4. Mowry Todd C.,CAX. Consistently specifying way destinations through prefetching hints. USP1998035732242.
  5. Teshima Tooru (Yokohama JPX) Urushihara Tetsuo (Sagamihara JPX). Data Processor system having look-ahead control. USP1988074755933.
  6. Inamoto Yasushi,JPX. Data access control system and computer-readable medium storing data access control program. USP2000046049891.
  7. Sokolov Daniel John. Disk drive selectively controlled to provide cache scan before seek. USP1999085937426.
  8. Sokolov Daniel John ; Swatosh Timothy. Disk drive with cache controlled adaptively for amount of prefetch. USP1999035890211.
  9. Sokolov Daniel John ; Williams Jeffrey L.. Disk drive with cache repeatedly accessed for a read command to provide prefetched data. USP1999075920887.
  10. Santhanam Vatsa (Campbell CA). Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instruc. USP1997125704053.
  11. Kayser Lyle D. ; Brown T. Gordon. Fold-out fin. USP2001016168111.
  12. Ji Brian ; Kirihata Toshiaki ; Mueller Gerhard ; Hanson David. Hierarchical prefetch for semiconductor memories. USP2000066081479.
  13. Larson Kenneth N. (Thousand Oaks CA) Davis John S. (Glendale CA) Bostick Lewis M. (Honolulu HI). Information exchange processor. USP1983114418382.
  14. Matsubara Kenji,JPX ; Kurihara Toshihiko,JPX ; Imori Hiromitsu,JPX. Information processing unit and method for controlling a hierarchical cache utilizing indicator bits to control content of prefetching operations. USP2000106131145.
  15. Yeh Tse-Yu ; Poplingher Mircea ; Fielden Kent G. ; Mulder Hans ; Gupta Rajiv ; Morris Dale ; Schlansker Michael. Instruction prefetch mechanism utilizing a branch predict instruction. USP1998045742804.
  16. Westberg Thomas E. (Sudbury MA). Intelligent cache memory and prefetch method based on CPU data fetching characteristics. USP1994115361391.
  17. Ramakrishnan Kadangode K. (Maynard MA) Biswas Prabuddha (Nashua NH). Managing the fetching and replacement of cache entries associated with a file system. USP1995025390318.
  18. Dubey Pradeep Kumar. Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative condit. USP1998065774685.
  19. Mulchandani Deepak (Austin TX) Gray Rand (Austin TX). Method and apparatus for restoring a target MCU debug session to a prior state. USP1997125701488.
  20. Tung Victor Wai Ner ; Sne Gal ; Scaringella Stephen Lawrence. Method and apparatus including a shared resource and multiple processors running a common control program accessing the. USP1999035884055.
  21. Blomgren James S.. Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield. USP1998105828578.
  22. Hoffman Roy L. (Pine Island MN) Houdek Merle E. (Rochester MN) Loen Larry W. (Rochester MN) Soltis Frank G. (Rochester MN). Multi-processor task dispatching apparatus. USP1983074394727.
  23. Sites Richard Lee ; Witek Richard T.. Prefetch instruction for improving performance in reduced instruction set processor. USP1998075778423.
  24. Vigil Peter J. ; Lederer Louis S. ; Blomgren James S.. Self-testing multi-processor die with internal compare points. USP1998035732209.
  25. Dean Mark E. (Austin TX). Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals. USP1996095553276.
  26. Carter John B. ; Davis Scott H. ; Dietterich Daniel J. ; Frank Steven J. ; Lee Hsin H.. Shared client-side web caching using globally addressable memory. USP2000026026474.
  27. Mayfield Michael John. System and method for diallocating stream from a stream buffer. USP1998045737565.
  28. Weisser Pirmin L.,DEX ; Vermeer Fulps V.,NLX ; King Edward C.. System and method for enhancing computer operation by prefetching data elements on a common bus without delaying bus ac. USP1998055751994.
  29. Weisser Pirmin L. (Unterkirnach DEX) Vermeer Fulps V. (Delft CA NLX) King Edward C. (Fremont CA). System and method for prefetching data from a main computer memory into a cache memory. USP1996065530941.
  30. Mehrotra Sharad. Voting data prefetch engine. USP1998105822790.