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System and method of computation in a programmable logic device using virtual instructions

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0541530 (2000-04-03)
발명자 / 주소
  • Sundararajarao Mohan
  • Stephen M. Trimberger
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Jeanette S. Harms
인용정보 피인용 횟수 : 122  인용 특허 : 33

초록

An FPGA configuration provides a virtual instruction. In a generic computation, the output pattern of a first instruction is compared to the input pattern of a second instruction. If the input and output patterns of the first and second instructions do not match, then a pattern manipulation instruct

대표청구항

1. A method for computation in a programmable logic device (PLD), the PLD including a logic plane and a plurality of memory planes, the method comprising:determining a first instruction of a computation task, wherein the first instruction has a first input pattern and a first output pattern; determi

이 특허에 인용된 특허 (33)

  1. Hsieh Hung-Cheng (San Jose CA), 5-Transistor memory cell which can be reliably read and written.
  2. Hsieh Hung-Cheng (Sunnyvale CA), 5-transistor memory cell with known state on power-up.
  3. Parlour David B. (Pittsburgh PA) Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Adaptive programming method for antifuse technology.
  4. Hsieh Wen-Jai (Vancouver WA) Jenq Yih-Chyun (Lake Oswego OR) Horng Chi-Song (Palo Alto CA), Apparatus for flexibly routing signals between pins of electronic devices.
  5. Bieber Larry C. (Simi Valley CA) Woodell Jack L. (La Canada CA), Apparatus for generating telex signaling sequences in a distributed processing telex exchange.
  6. Casselman Steven M., Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed.
  7. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Configuration modes for a time multiplexed programmable logic device.
  8. Zeilenga Jack H. (San Francisco CA) Hoenninger ; III John (Oakland CA), Continually loadable microcode store for MRI control sequencers.
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  11. Cloutier Jocelyn, FPGA-based processor.
  12. McCollum John L. (Saratoga CA), Field programmable digital signal processing array integrated circuit.
  13. Kim Young-ki,KRX, High speed ladder instruction process system for a programmable logic controller.
  14. Snider Gregory S. (Mountain View CA), IC which can be used as a programmable logic cell array or as a register file.
  15. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Integrated processor and programmable data path chip for reconfigurable computing.
  16. Takahashi Etsuo (Tokyo JPX), LSI logic synthesis device and method therefor.
  17. Chene Mon R. (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic placement using positionally asymmetrical partitioning algorithm.
  18. Trimberger Stephen M. (San Jose CA) Chene Mon-Ren (Cupertino CA), Logic placement using positionally asymmetrical partitioning method.
  19. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
  20. Trimberger Stephen M. (San Jose CA), Method for programming an FPLD using a library-based technology mapping algorithm.
  21. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
  22. Puhl Larry C. (Sleepy Hollow IL), Microprocessor with duplicate registers for processing interrupts.
  23. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  24. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.
  25. Lee Sai-keung (Milpitas CA), Programmable power supply level detection and initialization circuitry.
  26. Deglin Rene′ (Velizy-Villacoublay FRX) Reymond Gilbert (Malakoff FRX), Programmable sequential logic.
  27. Eng Robert C. (Boca Raton FL) Galella John W. (Boca Raton FL) McCrary Rex E. (Boca Raton FL) McDonald Mark G. (Delray Beach FL) Stelzer Eric H. (Boca Raton FL) Yentz Frederick C. (Boca Raton FL), Providing alternate bus master with multiple cycles of bursting access to local bus in a dual bus system including a pro.
  28. Crafts Harold S. (Colorado Springs CO) McKinley William W. (Fort Collins CO), Repeatedly programmable logic array using dynamic access memory.
  29. Trimberger Stephen M., Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page tab.
  30. Cox William D. (San Jose CA) Lehmann Eric E. (San Francisco CA) Lulla Mukesh T. (Santa Clara CA) Nathamuni Venkatesh R. (San Jose CA), Select set-based technology mapping method and apparatus.
  31. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Sequencer for a time multiplexed programmable logic device.
  32. Sawase Terumi (Hanno JPX) Hagiwara Yoshimune (Hachioji JPX) Nakamura Hideo (Tokyo JPX) Hatori Hiroyuki (Takasaki JPX) Baba Shirou (Tokorozawa JPX) Akao Yasushi (Kokubunji JPX), Single chip microprocessor for satisfying requirement specification of users.
  33. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.

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