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Self-protect thyristor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/74
  • H01L-031/119
출원번호 US-0424367 (2000-04-19)
우선권정보 DE-0021655 (1997-05-23)
국제출원번호 PCT/EP98/02305 (1998-04-18)
§371/§102 date 20000319 (20000319)
국제공개번호 WO98/53503 (1998-11-26)
발명자 / 주소
  • Rainer Constapel DE
  • Heinrich Sciilangenotto DE
  • Shuming Xu SG
출원인 / 주소
  • Vishay Semiconductor GmbH DE
대리인 / 주소
    Venable
인용정보 피인용 횟수 : 30  인용 특허 : 5

초록

With a self-protect thyristor, having a MOSFET (M1) that is connected in series with the thyristor and a second, self-controlled MOSFET (M2) between the p-base of the thyristor and the external cathode (KA), several unit cells for the thyristor are arranged parallel connected in a semiconductor wafe

대표청구항

1. A MOS gate-controlled thyristor with overcurrent protection, wherein several unit cells of the thyristor are arranged parallel-connected in a semiconductor wafer, comprising:a) respectively one n-emitter, one p-base, one n-base and one p-emitter, arranged between a cathode connection (KA) and an

이 특허에 인용된 특허 (5)

  1. Akatsuka Yasuo (Tokyo JPX), CMOS integrated circuit protected from latch-up phenomenon.
  2. Sakurai Naoki (Hitachi JPX) Sugawara Yoshitaka (Hitachi JPX), Power semiconductor device with low on-state voltage.
  3. Shires Mark R. (107 E. Fairmont Ave. Milwaukee WI 53217), Real-time electronically modulated cylindrical holographic autostereoscope.
  4. Steenblik Richard A. (Stone Mountain GA), Stereoscopic process and apparatus.
  5. Kirk Ronald L. (Findlay OH), Synthetic aperture based real time holographic imaging.

이 특허를 인용한 특허 (30)

  1. Salcedo, Javier Alejandro; Sweetland, Karl, Analog switch with high bipolar blocking voltage in low voltage CMOS process.
  2. Salcedo, Javier Alejandro; Casey, David; McCorkell, Graham, Apparatus and method for electronic circuit protection.
  3. Salcedo, Javier A.; Parthasarathy, Srivatsan, Apparatus and method for protection of precision mixed-signal electronic circuits.
  4. Salcedo, Javier Alejandro; Zhao, James; Luo, Juan, Apparatus and methods for transceiver interface overvoltage clamping.
  5. Clarke, David; Daly, Paul; McGuinness, Patrick; Stenson, Bernard; Deignan, Anne, Apparatus for electrostatic discharge protection.
  6. Salcedo, Javier Alejandro; Parthasarathy, Srivatsan, Apparatus for high speed signal processing interface.
  7. Salcedo, Javier Alejandro; Luo, Juan, Apparatus for transceiver signal isolation and voltage clamp.
  8. Salcedo, Javier Alejandro; Clarke, David J., Apparatuses for communication systems transceiver interfaces.
  9. Salcedo, Javier Alejandro; He, Linfeng, Apparatuses for communication systems transceiver interfaces.
  10. Salcedo, Javier A; Lynch, Michael; Moane, Brian, Bi-directional blocking voltage protection devices and methods of forming the same.
  11. Salcedo, Javier Alejandro; Parthasarathy, Srivatsan, Devices for monolithic data conversion interface protection and methods of forming the same.
  12. Salcedo, Javier Alejandro; Clarke, David J; Pfeifer, Jonathan Glen, Dual-tub junction-isolated voltage clamp devices for protecting low voltage circuitry connected between high voltage interface pins and methods of forming the same.
  13. Coyne, Edward John; McGuinness, Patrick Martin; Daly, Paul Malachy; Stenson, Bernard Patrick; Clarke, David J.; Bain, Andrew David; Lane, William Allan, Electrostatic protection device.
  14. Salcedo, Javier Alejandro; Pfeifer, Jonathan, High speed interface protection apparatus.
  15. Salcedo, Javier Alejandro; Pfeifer, Jonathan, High speed interface protection apparatus.
  16. Salcedo, Javier Alejandro, Interface protection device with integrated supply clamp and method of forming the same.
  17. Salcedo, Javier Alejandro, Interface protection device with integrated supply clamp and method of forming the same.
  18. Clarke, David J; Salcedo, Javier Alejandro; Moane, Brian B; Luo, Juan; Murnane, Seamus; Heffernan, Kieran K; Twomey, John; Heffernan, Stephen Denis; Cosgrave, Gavin Patrick, Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same.
  19. Clarke, David J.; Salcedo, Javier Alejandro; Moane, Brian B.; Luo, Juan; Murnane, Seamus; Heffernan, Kieran K.; Twomey, John; Heffernan, Stephen Denis; Cosgrave, Gavin Patrick, Junction-isolated blocking voltage structures with integrated protection structures.
  20. Zhao, James; Salcedo, Javier Alejandro, Low leakage bidirectional clamps and methods of forming the same.
  21. Salcedo, Javier A., Method and apparatus for protection and high voltage isolation of low voltage communication interface terminals.
  22. Kashyap, Avinash Srikrishnan; Sandvik, Peter Micah; McMahon, James Jay; Stevanovic, Ljubisa Dragoljub, Method and system for a semiconductor device with integrated transient voltage suppression.
  23. Salcedo, Javier A; Whitney, David Hall, Methods for protecting electronic circuits operating under high stress conditions.
  24. Coyne, Edward John, Overvoltage blocking protection device.
  25. Coyne, Edward John; Twomey, John; Whiston, Seamus P.; Clarke, David J.; McAuliffe, Donal P.; Lane, William Allan; Heffernan, Stephen Denis; Moane, Brian A.; Sweeney, Brian Michael; McGuinness, Patrick Martin, Overvoltage protection device and method.
  26. Majumdar,Gourab; Hatae,Shinji; Yamamoto,Akihisa, Power semiconductor device.
  27. Salcedo, Javier Alejandro; Parthasarathy, Srivatsan, Protection devices for precision mixed-signal electronic circuits and methods of forming the same.
  28. Salcedo, Javier A; Clarke, David J.; Cosgrave, Gavin P.; Huang, Yuhong, Protection systems for integrated circuits and methods of forming the same.
  29. Parthasarathy, Srivatsan; Salcedo, Javier A.; Zhang, Shuyun, Switching device for heterojunction integrated circuits and methods of forming the same.
  30. Peters,Christian, Thyristor structure and overvoltage protection configuration having the thyristor structure.
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