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UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
출원번호 US-0946810 (1997-10-08)
우선권정보 DE-0051075 (1996-12-09)
발명자 / 주소
  • Martin Vorbach DE
  • Robert Munch DE
출원인 / 주소
  • PACT GmbH DE
대리인 / 주소
    Kenyon & Kenyon
인용정보 피인용 횟수 : 99  인용 특허 : 105

초록

An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded fre

대표청구항

1. A configurable unit for processing numerical and logic operations, the configurable unit being controlled by a program load unit, comprising:a programmable arithmetic and logic unit for performing mathematical and logical functions; a respective synchronization unit in communication with the prog

이 특허에 인용된 특허 (105)

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  64. Vorbach, Martin, Methods and devices for treating and/or processing data.
  65. Weitkemper, Adam Clark; Molnar, Steven E.; French, Mark J.; Everitt, Cass W., Methods and systems for reusing memory addresses in a graphics system.
  66. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Methods and systems for transferring data between a processing device and external devices.
  67. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.
  68. Vorbach, Martin, Multi-processor with selectively interconnected memory units.
  69. Veeramachaneni,Venkat S.; Somasekhar,Dinesh, Multi-stage multiplexer.
  70. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.
  71. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
  72. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  73. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
  74. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
  75. Hirschsohn, Ian, Predictive resource allocation in computing systems.
  76. Vorbach,Martin; M체nch,Robert, Process for automatic dynamic reloading of data flow processors (DFPS) and units with two-or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like).
  77. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
  78. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
  79. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
  80. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
  81. Scheuermann, W. James, Processor for video data.
  82. Scheuermann, W. James, Processor for video data encoding/decoding.
  83. Vorbach, Martin, Reconfigurable elements.
  84. Vorbach, Martin, Reconfigurable elements.
  85. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
  86. Vorbach,Martin; M?nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
  87. Vorbach, Martin, Reconfigurable sequencer structure.
  88. Vorbach, Martin, Reconfigurable sequencer structure.
  89. Vorbach, Martin, Reconfigurable sequencer structure.
  90. Vorbach, Martin, Reconfigurable sequencer structure.
  91. Vorbach,Martin, Reconfigurable sequencer structure.
  92. Vorbach, Martin; Bretz, Daniel, Router.
  93. Vorbach,Martin; Bretz,Daniel, Router.
  94. Vorbach,Martin; M?nch,Robert, Run-time reconfiguration method for programmable units.
  95. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
  96. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas, Secure storage of program code for an embedded system.
  97. Jacob,Rojit; Chuang,Dan Minglun, System and method using embedded microprocessor as a node in an adaptable computing machine.
  98. Therien, Guy M.; Powell, Michael D.; Ramani, Venkatesh; Biswas, Arijit; Sotomayor, Guy G., Systems, methods and devices for determining work placement on processor cores.
  99. Jackson, James H.; Kraus, Thomas D., Wide connections for transferring data between PE's of an N-dimensional mesh-connected SIMD array while transferring operands from memory.
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