초록 ▼

A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic ele

A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

대표청구항 ▼

1. A field programmable gate array, comprising:a programmable interconnect structure; and a plurality of logic modules, each of said logic modules comprising: a first combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module a

1. A field programmable gate array, comprising:a programmable interconnect structure; and a plurality of logic modules, each of said logic modules comprising: a first combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure; a second combinatorial logic circuit having a plurality of input leads and an output lead, said input leads extending from said logic module and into said programmable interconnect structure; a first multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead being connected to said output lead of said first combinatorial logic circuit within said logic module, said second data input lead being connected to said output lead of said second combinatorial logic circuit within said logic module, said output lead extending from said logic module and into said programmable interconnect structure; a second multiplexer having a first data input lead, a second data input lead, a select input lead and an output lead, said first data input lead of said second multiplexer being connected to said output lead of said second combinatorial logic circuit within said logic module; a first sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said sequential logic element being coupled to said output lead of said first multiplexer, said data output lead extending from said logic module and into said programmable interconnect structure; and a second sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said second sequential logic element being coupled to said output lead of said second multiplexer, said data output lead of said second sequential logic element extending from said logic module and into said programmable interconnect structure.