초록 ▼

A method and apparatus for performing logic operations using dual-edge triggered dynamic logic families is provided. Further, a method for performing logic operations using a self-resetting mechanism within dual-edge triggered dynamic logic blocks is provided. Further, a dual-edge triggered dynamic

A method and apparatus for performing logic operations using dual-edge triggered dynamic logic families is provided. Further, a method for performing logic operations using a self-resetting mechanism within dual-edge triggered dynamic logic blocks is provided. Further, a dual-edge triggered dynamic circuit that maintains a duty cycle of an input signal at its output is provided. Further, a method for providing a buffer mechanism for clock distribution purposes is provided.

대표청구항 ▼

1. An output stage of a dynamic circuit, comprising:a first node that is triggered by a rising edge of an input signal; a second node that is triggered by a falling edge of the input signal; a first driver device that inputs a value on the first node; and a second driver device that inputs a value o

1. An output stage of a dynamic circuit, comprising:a first node that is triggered by a rising edge of an input signal; a second node that is triggered by a falling edge of the input signal; a first driver device that inputs a value on the first node; and a second driver device that inputs a value on the second node, wherein the first driver device and the second driver device selectively control an output of the dynamic circuit, and wherein at least one of a value on the first node and a value on the second node is dependent on the output.