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NROM cell with generally decoupled primary and secondary injection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/8238
출원번호 US-0519745 (2000-03-06)
발명자 / 주소
  • Boaz Eitan IL
출원인 / 주소
  • Saifun Semiconductors Ltd. IL
대리인 / 주소
    Eitan, Pearl, Latzer & Cohen-Zedek
인용정보 피인용 횟수 : 128  인용 특허 : 94

초록 ▼

A method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer. The step of decoupling can include the st

대표청구항

1. A method of creating a nitride, programmable read only memo (NROM) cell, the method comprising the step of:decoupling injection of channel hot electrons into a charge trapping layer of said NROM cell from injection of non-channel electrons into said charge trapping layer.

이 특허에 인용된 특허 (94)

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이 특허를 인용한 특허 (128)

  1. Forbes,Leonard, 4FEEPROM NROM memory arrays with vertical devices.
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  2. Forbes,Leonard, 4FEEPROM NROM memory arrays with vertical devices.
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  3. Forbes, Leonard, Apparatus and method for split gate NROM memory.
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  4. Forbes,Leonard, Apparatus and method for split transistor memory having improved endurance.
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  5. Forbes, Leonard, Apparatus and method for trench transistor memory having different gate dielectric thickness.
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  6. Dadashev, Oleg; Betser, Yoram; Maayan, Eduardo, Apparatus and methods for multi-level sensing in a memory array.
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  7. Forbes, Leonard, Ballistic direct injection NROM cell on strained silicon structures.
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  8. Forbes, Leonard, Ballistic direct injection NROM cell on strained silicon structures.
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  25. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
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  26. Forbes, Leonard, Fully depleted silicon-on-insulator CMOS logic.
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  27. Forbes,Leonard, Fully depleted silicon-on-insulator CMOS logic.
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  28. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg, Measuring and controlling current consumption and output current of charge pumps.
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  29. Polansky, Yan; Lavan, Avi, Memory array programming circuit and a method for using the circuit.
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  32. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
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  33. Forbes, Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
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  34. Forbes,Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
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  35. Forbes,Leonard, Memory device with high dielectric constant gate dielectrics and metal floating gates.
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  36. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
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  37. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide nanolaminates.
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  38. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide-conductor nanolaminates.
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  39. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide-conductor nanolaminates.
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  40. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide-conductor nanolaminates.
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  41. Forbes, Leonard; Ahn, Kie Y., Memory utilizing oxide-nitride nanolaminates.
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  42. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide-nitride nanolaminates.
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  43. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide-nitride nanolaminates.
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  44. Dadashev,Oleg, Method and apparatus for measuring charge pump output current.
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  45. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
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  46. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
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  47. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
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  48. Mihnea,Andrei; Chen,Chun, Method for erasing an NROM cell.
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  49. Guo, Jyh-Chyurn, Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions.
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  50. Forbes,Leonard, Method for fabricating semiconductor vertical NROM memory cells.
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  51. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet, Method for programming a reference cell.
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  52. Maayan,Eduardo; Eliyahu,Ron; Lann,Ameet; Eitan,Boaz, Method for programming a reference cell.
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  53. Mihnea, Andrei, Method for programming and erasing an NROM cell.
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  54. Mihnea, Andrei, Method for programming and erasing an NROM cell.
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  55. Mihnea, Andrei, Method for programming and erasing an NROM cell.
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  56. Mihnea,Andrei, Method for programming and erasing an NROM cell.
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  57. Mihnea,Andrei, Method for programming and erasing an NROM cell.
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  58. Mihnea,Andrei, Method for programming and erasing an NROM cell.
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