$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of copper electroplating 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0739930 (2000-12-18)
발명자 / 주소
  • Valery M. Dubin
  • Dave W. Jentz
  • Christopher Collazo-Davila
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 70  인용 특허 : 3

초록

An electroplating process for filling damascene structures on substrates, such as wafers having partially fabricated integrated circuits thereon, includes immersing a substrate, under bias, into a copper plating solution to eliminate thin seed layer dissolution and reduce copper oxide, an initiation

대표청구항

1. A method of forming copper interconnect, comprising:forming trenches in a dielectric layer disposed on a wafer; forming a barrier layer over the trenches and dielectric layer immersing the wafer, under bias, in a plating solution; performing a first plating operation at a forward current density

이 특허에 인용된 특허 (3)

  1. Sergey D. Lopatin ; John A. Iacoponi, Method for ramped current density plating of semiconductor vias and trenches.
  2. Ueno Kazuyoshi,JPX, Method of electroplating copper interconnects.
  3. Lopatin Sergey D. ; Buynoski Matthew S., Time ramped method for plating of high aspect ratio semiconductor vias and channels.

이 특허를 인용한 특허 (70)

  1. Herchen, Harald, Anode isolation by diffusion differentials.
  2. Yang, Michael X.; Kovarsky, Nicolay Y., Anolyte for copper plating.
  3. Yang,Michael X.; Kovarsky,Nicolay Y., Anolyte for copper plating.
  4. Cohen, Uri, Apparatus for enhanced electrochemical deposition.
  5. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  6. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  7. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  8. Weidman, Timothy W.; Wijekoon, Kapila P.; Zhu, Zhize; Gelatos, Avgerinos V. (Jerry); Khandelwal, Amit; Shanmugasundram, Arulkumar; Yang, Michael X.; Mei, Fang; Moghadam, Farhad K., Contact metallization scheme using a barrier layer over a silicide layer.
  9. Chen, Ling; Ganguli, Seshadri; Marcadal, Christophe; Cao, Wei; Mosely, Roderick C.; Chang, Mei, Copper interconnect barrier layer structure and formation method.
  10. Webb, Eric; Reid, Jon; Takada, Yuichi; Archer, Timothy, Deposit morphology of electroplated copper.
  11. Webb, Eric; Reid, Jonathan D.; Takada, Yuichi; Archer, Timothy, Deposit morphology of electroplated copper.
  12. Zheng, Bo; He, Renren; Dixit, Girish, ECP gap fill by modulating the voltate on the seed layer to increase copper concentration inside feature.
  13. Yang,Michael X.; Lubomirsky,Dmitry; Dordi,Yezdi; Singh,Saravjeet; Tulshibagwale,Sheshraj; Kovarsky,Nicolay, Electrochemical processing cell.
  14. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  15. Stewart, Michael P.; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Eaglesham, David J., Electroless deposition process on a silicon contact.
  16. Cohen, Uri, Electroplated metallic conductors.
  17. Webb, Eric G.; Reid, Jonathan D.; Sukamto, John H.; Varadarajan, Sesha; Pollack, Margolita M.; Buckalew, Bryan L.; Majid, Tariq, Electroplating using DC current interruption and variable rotation rate.
  18. Cohen, Uri, Enhanced electrochemical deposition (ECD) filling of high aspect ratio openings.
  19. Cohen, Uri, Enhanced electrochemical deposition filling.
  20. Cohen,Uri, Filling high aspect ratio openings by enhanced electrochemical deposition (ECD).
  21. Yang, Chih Chao; Klymko, Nancy R.; Parks, Christopher C.; Wong, Keith Kwong Hon, Formation of oxidation-resistant seed layer for interconnect applications.
  22. Yang,Chih Chao; Klymko,Nancy R.; Parks,Christopher C.; Wong,Keith Kwong Hon, Formation of oxidation-resistant seed layer for interconnect applications.
  23. Zhu, Mei; Wang, Zhihai, High frequency electrochemical deposition.
  24. Xu, Xingling; Webb, Eric, High speed copper plating bath.
  25. Cohen, Uri, High speed electroplating metallic conductors.
  26. Dubin,Valery M., Integrated circuit with metal layer having carbon nanotubes and methods of making same.
  27. Kruglick, Ezekiel, Magnetic electro-plating.
  28. Opocensky, Edward C.; Spurlin, Tighe A.; Reid, Jonathan D., Method and apparatus for characterizing metal oxide reduction.
  29. Spurlin, Tighe A.; Antonelli, George Andrew; Doubina, Natalia; Duncan, James E.; Reid, Jonathan D.; Porter, David, Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer.
  30. Hey, Peter; Kwak, Byung-Sung Leo, Method and apparatus to overcome anomalies in copper seed layers and to tune for feature size and aspect ratio.
  31. Dordi, Yezdi N.; Stevens, Joseph J.; Sugarman, Michael N., Method and associated apparatus for tilting a substrate upon entry for metal deposition.
  32. Lopatin,Sergey; Shanmugasundram,Arulkumar; Lubomirsky,Dmitry; Pancham,Ian A., Method for forming CoWRe alloys by electroless deposition.
  33. Ajiki,Shuichi; Kashima,Toshinobu; Akagi,Tsutomu, Method for producing color-converting light-emitting device using electrophoresis.
  34. Albrecht, Anton; Dautl, Thomas; Oezcan, Oemer-Refik; Pillhoefer, Horst, Method for producing of a galvanic coating.
  35. Zheng, Bo; Bajaj, Rajeev; Wang, Zhonghui Alex, Method for regulating the electrical power applied to a substrate during an immersion process.
  36. Zheng, Bo; Wang, Hougong; Dixit, Girish; Chen, Fusen, Method of application of electrical biasing to enhance metal deposition.
  37. Uzoh,Cyprian E.; Aksu,Serdar; Basol,Bulent M., Method of electroplating copper layers with flat topography.
  38. Chong, Chin Hui; Lee, Choon Kuan, Method of manufacturing an interposer.
  39. Hafezi, Hooman; Rosenfeld, Aron; Yang, Michael X., Method to deposit organic grafted film on barrier layer.
  40. Cohen, Uri, Methods for activating openings for jets electroplating.
  41. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  42. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  43. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  44. Spurlin, Tighe A.; Lambert, Darcy E.; Singhal, Durgalakshmi; Antonelli, George Andrew, Methods for reducing metal oxide surfaces to modified metal surfaces using a gaseous reducing environment.
  45. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filing vias in microelectronic devices.
  46. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filling vias in microelectronic devices.
  47. Clark, Douglas; Oliver, Steven D.; Kirby, Kyle K.; Dando, Ross S., Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces.
  48. Hiatt, William M.; Dando, Ross S., Microfeature workpieces and methods for forming interconnects in microfeature workpieces.
  49. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  50. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  51. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  52. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.
  53. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.
  54. Leavy, Montray, Multi material secondary metallization scheme in MEMS fabrication.
  55. Yang,Michael X.; Xi,Ming; Ellwanger,Russell C.; Britcher,Eric B.; Donoso,Bernardo; Pang,Lily L.; Sherman,Svetlana; Ho,Henry; Nguyen,Anh N.; Lerner,Alexander N.; D'Ambra,Allen L.; Shanmugasundram,Arul, Multi-chemistry plating system.
  56. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  57. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  58. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  59. Buckalew, Bryan L.; Rea, Mark L., Pretreatment method for photoresist wafer processing.
  60. Buckalew, Bryan L.; Rea, Mark L., Pretreatment method for photoresist wafer processing.
  61. Lubomirsky, Dmitry; Weidman, Timothy W.; Shanmugasundram, Arulkumar; Kovarsky, Nicolay Y.; Wijekoon, Kapila, Process for electroless copper deposition.
  62. Richardson, Thomas B.; Abys, Joseph A.; Shao, Wenbo; Wang, Chen; Paneccasio, Vincent; Wang, Cai; Lin, Sean Xuan; Antonellis, Theodore, Process for filling vias in the microelectronics.
  63. Mak, Alfred W.; Chang, Mei; Byun, Jeong Soo; Chung, Hua; Sinha, Ashok; Kori, Moris, System and method to form a composite film stack utilizing sequential deposition techniques.
  64. Watkins, Charles M.; Hiatt, William M., System and methods for forming apertures in microfeature workpieces.
  65. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  66. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  67. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  68. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  69. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  70. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로