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Three-dimensional multichip module 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0932859 (2001-08-17)
발명자 / 주소
  • Paul A. Farrar
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Knobbe, Martens, Olson & Bear, LLP
인용정보 피인용 횟수 : 26  인용 특허 : 14

초록

A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted to the exterior faces of the base structure. The multichip module may incorporate memory chips, processor chips, logic chips, A to D conve

대표청구항

1. A multichip module comprising:a plurality of semiconductor chips stacked and secured together to form a base structure wherein the base structure has a first lateral face that is comprised of a portion of each chip; an exterior semiconductor chip mounted to the first lateral face of the base stru

이 특허에 인용된 특허 (14)

  1. Go Tiong C. (El Toro CA), High-density electronic modules-process and product.
  2. Carson John C. (Corona del Mar CA) Clark Stewart A. (Irvine CA), High-density electronic processing package-structure and fabrication.
  3. Bertin Claude L. (So. Burlington VT) Farrar Paul A. (So. Burlington VT) Kelley ; Jr. Gordon A. (Essex Junction VT) Miller Christopher P. (Underhill VT), Method and apparatus for a stress relieved electronic module.
  4. Belanger Robert J. (Costa Mesa CA) Bisignano Alan G. (Anaheim CA), Method for fabricating modules comprising uniformly stacked, aligned circuit-carrying layers.
  5. Farrar Paul A., Method of forming foamed polymeric material for an integrated circuit.
  6. Bertin Claude Louis ; Hedberg Erik Leigh ; Leas James Marc ; Voldman Steven Howard, Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection f.
  7. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  8. Bernhardt Anthony F. (Berkeley CA), Microchannel cooling of face down bonded chips.
  9. Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Howell Wayne J. (South Burlington VT) Miller Christopher P. (Underhill VT) Perlman David J. (Wappingers Falls NY), Polyimide-insulated cube package of stacked semiconductor device chips.
  10. Ludwig David E. (Irvine CA) Saunders Christ H. (Laguna Niguel CA) Some Raphael R. (Williston VT) Stuart John J. (Newport Beach CA), Stack of IC chips in lieu of single IC chip.
  11. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  12. Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT) van der Hoeven Willem B. (Jericho VT) Whi, Three dimensional multichip package methods of fabrication.
  13. Bernhardt Anthony F. (Berkeley CA) Petersen Robert W. (Pleasanton CA), Three dimensional, multi-chip module.
  14. Bertin Claude L. (South Burlington) Farrar ; Sr. Paul A. (South Burlington) Kalter Howard L. (Colchester) Kelley ; Jr. Gordon A. (Essex Junction) van der Hoeven Willem B. (Jericho) White Francis R. (, Three-dimensional multichip packages and methods of fabrication.

이 특허를 인용한 특허 (26)

  1. Farrar, Paul A., Angled edge connections for multichip structures.
  2. Farrar, Paul A., Angled edge connections for multichip structures.
  3. Farrar, Paul A., Apparatus and method for high density multi-chip structures.
  4. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  5. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  6. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
  7. Farrar, Paul A., Insulators for high density circuits.
  8. Farrar, Paul A., Insulators for high density circuits.
  9. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  10. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  11. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  12. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  13. Farrar,Paul A., Integrated circuit cooling system and method.
  14. Farrar,Paul A., Integrated circuit cooling system and method.
  15. Farrar, Paul A., Low dielectric constant STI with SOI devices.
  16. Farrar, Paul A., Memory system with conductive structures embedded in foamed insulator.
  17. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  18. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  19. Farrar, Paul A., Polynorbornene foam insulation for integrated circuits.
  20. Shi, Xunqing; Xie, Bin; Chung, Chang Hwa, Semiconductor chip with through-silicon-via and sidewall pad.
  21. Barth, Hans-Joachim, Three-dimensional multichip module.
  22. Barth, Hans-Joachim, Three-dimensional multichip module.
  23. Barth, Hans-Joachim, Three-dimensional multichip module.
  24. Barth, Hans-Joachim, Three-dimensional multichip module.
  25. Farrar,Paul A., Three-dimensional multichip module.
  26. Garth,Emory, Three-dimensional stack manufacture for integrated circuit devices and method of manufacture.
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