초록 ▼

A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhes

A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer 220 and a barrier metal layer 230 over a substrate 10. The barrier layer 230 is polished and activated. Next, the aluminum layer 220 and the barrier metal layer 230 are patterned. A metal layer 240 is electroless deposited. Next a solder bump 250 is formed over the electroless metal layer 240.

대표청구항 ▼

1. A method for forming an interconnect by depositing selectively by electroless deposition a metal using a palladium silicide seed layer comprising the steps of:a) providing a semiconductor structure; b) forming a barrier layer over said semiconductor structure; c) forming an adhesion layer over sa

1. A method for forming an interconnect by depositing selectively by electroless deposition a metal using a palladium silicide seed layer comprising the steps of:a) providing a semiconductor structure; b) forming a barrier layer over said semiconductor structure; c) forming an adhesion layer over said barrier metal layer, said adhesion layer is comprised of polysilicon; d) sputter depositing a palladium layer over said adhesion layer; e) annealing said palladium layer to form a palladium silicide layer; f) patterning said palladium silicide layer to form palladium silicide interconnect patterns; g) patterning said barrier layer using said palladium silicide interconnect patterns as an etch mask forming barrier layer interconnect patterns; h) selectively electroless depositing a metal layer on said palladium silicide line patterns to form an interconnect; said metal layer composed of a material selected from the group consisting of Ni, Cu, and palladium, whereby said metal layer was deposited without activating said palladium silicide line.