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Thin film metal barrier for electrical interconnections 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/40
출원번호 US-0759258 (2001-01-16)
발명자 / 주소
  • Cyril Cabral, Jr.
  • Patrick William Dehaven
  • Daniel Charles Edelstein
  • David Peter Klaus
  • James Manley Pollard, III
  • Carol L. Stanis
  • Cyprian Emeka Uzoh
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Connolly Bove Lodge & Hutz
인용정보 피인용 횟수 : 29  인용 특허 : 8

초록

An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also

대표청구항

1. An interconnect structure comprising:a first insulation layer having an upper and lower surface and having a plurality of grooves formed in said upper surface, some of said grooves having regions extending to said lower surface to expose respective conducting surfaces in a second interconnect str

이 특허에 인용된 특허 (8)

  1. Chan Lap ; Zheng Jia Zhen,SGX, Barrier layer.
  2. Beyer Klaus D. (Poughkeepsie NY) Guthrie William L. (Poughkeepsie NY) Makarewicz Stanley R. (New Windsor NY) Mendel Eric (Poughkeepsie NY) Patrick William J. (Newburgh NY) Perry Kathleen A. (Lagrange, Chem-mech polishing method for producing coplanar metal/insulator films on a substrate.
  3. Crank Sue E. (Coppell TX), Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer.
  4. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  5. Colgan Evan G. (Wappingers Falls NY) Fryer Peter M. (Mamaroneck NY), Method of making Alpha-Ta thin films.
  6. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.
  7. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
  8. Colgan Evan G. (Wappingers Falls NY) Fryer Peter M. (Mamaroneck NY), Structure and method of making Alpha-Ta in thin films.

이 특허를 인용한 특허 (29)

  1. Yang, Chih-Chao; Bonilla, Griselda; Lin, Qinghuang; Spooner, Terry A., Adhesion enhancement for metal/dielectric interface.
  2. Yang,Chih Chao; Bonilla,Griselda; Lin,Qinghuang; Spooner,Terry A., Adhesion enhancement for metal/dielectric interface.
  3. Barth,Hans Joachim; Holz,Juergen, Barrier layer for conductive features.
  4. Barth, Hans-Joachim; Holz, Juergen, Barrier layers for conductive features.
  5. Erb,Darrell M.; Avanzino,Steven C.; Woo,Christy Mei Chu, Composite tantalum nitride/tantalum copper capping layer.
  6. Yang, Chih-Chao; Hsu, Louis C.; Joshi, Rajiv V., Dielectric interconnect structures and methods for forming the same.
  7. Yang,Chih Chao; Hsu,Louis C.; Joshi,Rajiv V., Dielectric interconnect structures and methods for forming the same.
  8. Daubenspeck,Timothy H.; Gambino,Jeffrey P.; Muzzy,Christopher D.; Sauter,Wolfgang, Electrical interconnection structure formation.
  9. Daubenspeck,Timothy Harrison; Gambino,Jeffrey Peter; Muzzy,Christopher David; Sauter,Wolfgang, Electrical interconnection structure formation.
  10. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  11. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  12. Yang, Chih-Chao; Edelstein, Daniel C.; Nogami, Takeshi, Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application.
  13. Yang, Chih-Chao; Edelstein, Daniel C.; Nogami, Takeshi, Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application.
  14. Edelstein,Daniel C.; Li,Baozhen; Sullivan,Timothy D., Liner with improved electromigration redundancy for damascene interconnects.
  15. Colburn,Matthew E., Method for improved process latitude by elongated via integration.
  16. Colburn,Matthew E., Method for improved process latitude by elongated via integration.
  17. Edelstein, Daniel C.; Yang, Chih-Chao, Method of forming resistors with controlled resistivity.
  18. Edelstein, Daniel C.; Yang, Chih-Chao, Method of forming tunable resistor with curved resistor elements.
  19. Yang, Chih-Chao; Hsu, Louis C.; Joshi, Rajiv V., Methods for forming dielectric interconnect structures.
  20. Yang, Chih-Chao; Shaw, Thomas M., Redundant metal barrier structure for interconnect applications.
  21. Yang, Chih-Chao; Shaw, Thomas M., Redundant metal barrier structure for interconnect applications.
  22. Edelstein, Daniel C.; Yang, Chih-Chao, Resistors with controlled resistivity.
  23. Kishida, Takenobu; Tada, Shinya; Ikeda, Atsushi; Harada, Takeshi; Sugihara, Kohei, Semiconductor device and method for fabricating the same.
  24. Kishida, Takenobu; Tada, Shinya; Ikeda, Atsushi; Harada, Takeshi; Sugihara, Kohei, Semiconductor device including a layer having a β-crystal structure.
  25. Moon, Bum Ki; Shum, Danny Pak-Chum; Chae, Moosung, Semiconductor devices and methods of manufacture thereof.
  26. Mehta, Sanjay C.; Edelstein, Daniel C.; Fitzsimmons, John A.; Grunow, Stephan; Nye, III, Henry A.; Rath, David L., Structure and method of chemically formed anchored metallic vias.
  27. Purushothaman, Sampath; Sankarapandian, Muthumanickam; Shobha, Hosadurga; Spooner, Terry A., Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair.
  28. Edelstein, Daniel C.; Yang, Chih-Chao, Tunable resistor with curved resistor elements.
  29. Edelstein, Daniel C.; Yang, Chih-Chao, Tunable resistor with curved resistor elements.
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