초록 ▼

An integrated circuit, including but not limited to a memory device, receives an externally provided voltage signal and selectively adjusts the timing of internal control signals. An external signal selects between two possible pre-determined delay paths. The delay paths are adjusted using fuse circ

An integrated circuit, including but not limited to a memory device, receives an externally provided voltage signal and selectively adjusts the timing of internal control signals. An external signal selects between two possible pre-determined delay paths. The delay paths are adjusted using fuse circuitry which can be programmed by the manufacturer prior to implementation by a user. The delay path adjustment feature is particularly applicable to adjusting output signal timing to allow the integrated circuit to be operated in an environment which requires slower communications speeds. The same integrated circuit, therefore, can also be implemented in an environment which allows for faster communications speeds.

대표청구항 ▼

1. An integrated circuit memory device comprising:an input connection for receiving an externally provided voltage signal; read circuitry for reading data stored in the memory device; data output circuitry for providing data read from the memory device to an external connection; internal circuitry f

1. An integrated circuit memory device comprising:an input connection for receiving an externally provided voltage signal; read circuitry for reading data stored in the memory device; data output circuitry for providing data read from the memory device to an external connection; internal circuitry for providing an internal signal to control the data output circuitry; an adjustable delay circuit for receiving the internal signal as an input signal and providing an output signal at an output node, the adjustable delay circuit has a plurality of possible delay paths for communicating the input signal to the output node, the plurality of possible delay paths including a plurality of delay circuits each having at least two output connections and a select circuit, at least one of the at least two output connections being electrically common with the output node; control circuitry selectively coupled to receive the externally provided voltage signal; and an encoded signal output from the control circuitry that is decoded by each of the select circuits to determine which of the at least two output connections the input signal will be communicated along en route to the output node, wherein an operating speed of the data output circuitry is adjusted by the internal signal.